Datasheet

32
8024A–AVR–04/08
ATmega8HVA/16HVA
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, or clear the CLK-
PCE bit.
• Bit 1:0 – CLKPS1:0: Clock Prescaler Select Bit 1..0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table 9-3 on page 32. Note that writing to the System Clock Prescaler Select bits will abort any
ongoing VADC conversion.
Note: 1. Reserved values should not be written to CLKPS1..0.
Note: 1. When changing Prescaler value, the VADC Prescaler will automatically change frequency of
the VADC clock and abort any ongoing conversion.
9.13.4 OSICSR – Oscillator Sampling Interface Control and Status Register
• Bits 7:5,3:2 – RES: Reserved bits
These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero.
Table 9-3. System Clock Prescaler Select
CLKPS1 CLKPS0 Clock Division Factor
00Reserved
(1)
012
104
118
Table 9-4. VADC Clock Prescaling
(1)
CLKPS1 CLKPS0 VADC Division Factor
00Reserved
014
102
111
Bit 7 6 5 4 3 2 1 0
0x17 (0x37) – – – OSISEL0 – – OSIST OSIEN OSICSR
Read/Write R R R R/W R R R R/W
Initial Value 0 0 0 0 0 0 0 0