Datasheet

24
8024A–AVR–04/08
ATmega8HVA/16HVA
9. System Clock and Clock Options
9.1 Clock Systems and their Distribution
Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in ”Power Manage-
ment and Sleep Modes” on page 34. The clock systems are detailed below.
Figure 9-1. Clock Distribution
9.1.1 CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
9.1.2 I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules. The I/O clock is also used by the Exter-
nal Interrupt module, but note that some external interrupts are detected by asynchronous logic,
allowing such interrupts to be detected even if the I/O clock is halted.
9.1.3 Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
9.1.4 Voltage ADC Clock – clk
VADC
The Voltage ADC is provided with a dedicated clock domain. The VADC clock is automatically
prescaled relative to the System Clock Prescalers setting by the VADC Prescaler, giving a fixed
VADC clock at 1 MHz.
Ultra Low Power
RC Oscillator
Watchdog Timer Battery Protection Reset Logic
CPU
CORE
RAM
FLASH and
EEPROM
Voltage
ADC
Other I/O
Modules
Coulomb Counter
ADC
AVR
Clock Control
Fast RC
Oscillator
clk
CPU
clk
FLASH
clk
VADC
clk
I/O
1/4
System Clock
Prescaler
VADC
Prescaler
Oscillator Sampling
Interface
Slow RC
Oscillator
clk
CCADC