Datasheet

171
8024A–AVR–04/08
ATmega8HVA/16HVA
29.7 SPI Timing Characteristics
See Figure 29-1 on page 171 and Figure on page 172 for details.
Note: 1. Refer to ”Serial Programming” on page 151 for serial programming requirements.
Figure 29-1. SPI Interface Timing Requirements (Master Mode)
Table 29-7. SPI Timing Parameters
Description Mode
Min Typ Max Units
1 SCK period Master See Figure
ns
2 SCK high/low Master 50% duty
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • t
sck
7 SCK to out Master 10
8 SCK to out high Master 10
9SS
low to out Slave 15
10 SCK period Slave 4 • t
ck
+ 40 ns
11 SCK high/low
(1)
Slave 2 • t
ck
+ 20 ns
12 Rise/Fall time Slave 1.6 µs
13 Setup Slave 10
ns
14 Hold Slave t
ck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS
high to tri-state Slave 10
18 SS low to SCK Slave 20
MOSI
(
Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
61
22
345
8
7