Datasheet

152
8024A–AVR–04/08
ATmega8HVA/16HVA
Figure 27-1. Serial Programming and Verify.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on OSCSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low: > 2.2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
>= 12 MHz
High: > 2.2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
>= 12 MHz
27.6.1 Serial Programming Algorithm
When writing serial data to the ATmega8HVA/16HVA, data is clocked on the rising edge of SCK.
When reading data from the ATmega8HVA/16HVA, data is clocked on the falling edge of SCK.
See ”Serial Programming” on page 172 for timing details.
To program and verify the ATmega8HVA/16HVA in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in Table 27-10 on page 154):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET
must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
Table 27-8. Pin Mapping Serial Programming
Symbol Pins I/O Description
SCK PB1 I Serial Clock
MOSI PB2 I Serial Data in
MISO PB3 O Serial Data out
VCC
GND
SCK
MISO
MOSI
RESET
+3.0 - 4.5V