Datasheet

137
8024A–AVR–04/08
ATmega8HVA/16HVA
Figure 24-3. Switching NFET on and off during NORMAL operation
24.3 DUVR – Deep Under-Voltage Recovery Mode operation
The purpose of DUVR mode is to control the Charge FET so that the VFET voltage is above the
minimum operating voltage while charging cells below minimum operating voltage. This is useful
when the cell has been discharged below the minimum operating voltage of the chip. In DUVR
mode the Charge FET is switched partly on to provide a suitable voltage drop between the cell
voltage and the VFET terminal. As the cell voltage increases, the voltage drop across the
Charge FET will gradually decrease until the Charge FET is switched completely on. This means
that for high cell voltages, DUVR mode operation is equivalent to normal enabling of the Charge
FET (CFE=1).
ATmega8HVA/16HVA should operate in DUVR mode until software detects that the cell has
recovered from Deep Under-Voltage condition. When the cell has recovered from Deep Under-
Voltage condition, software should first set CFE=1. This is safe now since the cell voltage is
above minimum operating voltage. After that software should disable DUVR mode by setting
DUVRD = 1.
If both DUVRD and CFE bit is set before the cell voltage is above minimum operating voltage,
the VFET voltage will drop and the chip will enter BOD reset and switch off both the Charge- and
Discharge FET. Switching off the FET’s will cause the VFET voltage to rise again so that the
chip restarts from BOD reset, with DUVRD = 0 and CFE = 0 (default values). To avoid this, soft-
ware must always check the cell voltage by V-ADC measurements before setting CFE=1.
DUVR mode is default enabled after reset. However, while the chip is in reset state, DUVR
mode is disabled. This is a safety feature that ensures that the Charge FET will not be switched
on until the Charge Over-current Protection is operating. This implies that the DUVR mode will
be disabled from the time that a charger is connected until the selected start-up time expired.
During this period, the VFET voltage will be higher than the normal VFET Level in DUVR mode.
For more details about DUVR mode, refer to application note AVR354.
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