Datasheet

131
8024A–AVR–04/08
ATmega8HVA/16HVA
23.9.6 BPSCD – Battery Protection Short-circuit Detection Level Register
• Bits 7:0 – SCDL7:0: Short-circuit Detection Level
These bits sets the R
SENSE
voltage level for detection of Short-circuit in the discharge direction,
as defined in Table 23-5 on page 132.
Note: Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPSCD register is written. Any
writing to the BPSCD register during this period will be ignored.
23.9.7 BPDOCD – Battery Protection Discharge-Over-current Detection Level Register
• Bits 7:0 – DOCDL7:0: Discharge Over-current Detection Level
These bits sets the R
SENSE
voltage level for detection of Discharge Over-current, as defined in
Table 23-5 on page 132.
Note: Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPDOCD register is written. Any
writing to the BPDOCD register during this period will be ignored.
23.9.8 BPCOCD – Battery Protection Charge-Over-current Detection Level Register
• Bits 7:0 –COCDL7:0: Charge Over-current Detection Level
These bits sets the R
SENSE
voltage level for detection of Charge Over-current, as defined in
Table 23-5 on page 132.
Note: Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPCOCD register is written. Any
writing to the BPCOCD register during this period will be ignored.
Bit 76543210
(0xF5) SCDL[7:0] BPSCD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value11110011
Bit 76543210
(0xF6) DOCDL[7:0] BPDOCD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 1 1 1 1 0 0 1 1
Bit 76543210
(0xF7) COCDL[7:0] BPCOCD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 1 1 1 1 0 0 1 1