Datasheet

127
8024A–AVR–04/08
ATmega8HVA/16HVA
tection interrupt request to the CPU. This interrupt can wake up the CPU from any operation
mode, except Power-off. The interrupt flags are cleared by writing a logic ‘1’ to their bit locations
from the CPU.
Note that there are neither flags nor status bits indicating that the chip has entered the Power Off
mode. This is because the CPU is powered down in this mode. The CPU will, however be able
to detect that it came from a Power-off situation by monitoring CPU reset flags when it resumes
operation.
23.9 Register Description
23.9.1 BPPLR – Battery Protection Parameter Lock Register
• Bit 7:2 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 1 – BPPLE: Battery Protection Parameter Lock Enable
• Bit 0 – BPPL: Battery Protection Parameter Lock
The BPCR, BPHCTR, BPOCTR, BPSCTR, BPDHCD, BPCHCD, BPDOCD, BPCOCD and
BPSCD Battery Protection registers can be locked from any further software updates. Once
locked, these registers cannot be accessed until the next hardware reset. This provides a safe
method for protecting the registers from unintentional modification by software runaway. It is rec-
ommended that software sets these registers shortly after reset, and then protect the registers
from further updates.
To lock these registers, the following algorithm must be followed:
1. In the same operation, write a logic one to BPPLE and BPPL.
2. Within the next four clock cycles, in the same operation, write a logic zero to BPPLE and
a logic one to BPPL.
23.9.2 BPCR – Battery Protection Control Register
• Bits 7:6 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 5 – Res: Reserved Bits
This bit are reserved and will always read as one.
Bit 76543210
(0xFE) ––––––BPPLEBPPLBPPLR
Read/Write RRRRRRR/WR/W
Initial Value00000000
Bit 76543210
(0xFD) – – – SCD DOCD COCD DHCD CHCD BPCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value00100000