Datasheet

121
8024A–AVR–04/08
ATmega8HVA/16HVA
Figure 22-1. Voltage regulator block diagram, combined Step-up and Linear mode
Figure 22-2. Voltage regulator operation and reset signals as a function of rising and falling
input voltage for 1-cell operation.
VIN
VREF
ENABLE
VREG
CHARGER
DETECT
VREF
V
FET
B
AT T
Voltage
Regulator
CLK
CLK
NFET
DRIVER
DUALC_MODE
STARTED
STEP_UP_EN
LIN_EN
VIN
VREF
ENABLE
STARTED
PV_CHECK
DUALC_MODE
ENABLE
VREF
VIN
VOUT
CF1P
CF1N
CF2P
CF2N
CLK
ENABLE
VREF
VIN
VOUT
CF1
CF2
CRE
G
DCDC-CTRL
STEP-UP-REG
LIN-REG
disabled disabled
R
egulator operation
DUVR mode
Power-on Reset
Chip Reset
charge pumping linear operation
5V
3,3V
V
DUVR
4/8/16/32/64/128/256/512 ms
charge pumping
SW controlled
Charger is connected
V
IN
V
REG
T
POT