Datasheet

120
8024A–AVR–04/08
ATmega8HVA/16HVA
22. Voltage Regulator
22.1 Features
• 3.3V fixed output voltage
• Automatic selection of Step-up or Linear Regulation depending on VFET voltage.
• Fixed Linear Regulation mode can be selected for 2-cell applications
• Battery Pack Short mode allowing large voltage drop at VFET without pulling VREG low.
22.2 Overview
The Voltage Regulator is a Combined Step-up and Linear Voltage Regulator. This allows the
same Voltage Regulator module to be used efficiently for a large range of input voltages.
A built in Charge-pump with external capacitors is combined with a linear regulator to keep a
constant output voltage for input voltages in the range 1.8 - 9.0V.
Figure 22-1 on page 121 shows the Voltage Regulator block diagram with external components
for combined Step-up and Linear mode. Figure 22-2 on page 121 shows the regulated voltage
VREG as a function of the input voltage VFET for 1-cell operation. When the VFET is sufficiently
high, the regulator switches automatically to linear operation. When VFET drops below a certain
level the regulator automatically switch back to step-up regulation. The different reset sources
during initialisation and shut down is also shown.
Figure 22-3 on page 122 shows the Voltage Regulator block diagram with external components
for Linear mode only, intended for 2-cell applications. In Linear mode only, the input voltage
range is 3.6 - 9.0V. In this case, no external fly capacitors are needed, and CF1N should be
grounded. Figure 22-4 on page 122 illustrates this operation.
In case of battery pack shortening, the voltage at the input of the regulator will drop quickly. If it
drops below minimum operating voltage, the voltage regulator can no longer supply internal or
external circuitry. However, the output voltage will not be pulled down by this incident, and the
external CREG capacitor can supply the circuitry for a time given by the size of the capacitor and
the total current consumption during the same period. VREG must stay above the Brown-Out
Threshold to avoid BOD reset. If a battery pack short occurs when VREG is equal to 3.3V and
the BOD level is 2.9V, the chip can continue operation for a time given by:
where I
AVG
represents the average current drawn from CREG. For CREG = 2.2 µF and
I
AVG
= 100 µA, this time equals 8.8 ms. The Voltage Regulator Monitor will detect if a short-circuit
has occured, allowing SW to minimize I
AVG
.
When charging deeply over-discharged cells, the FET Driver will be operated in Deep Under-
Voltage Recovery (DUVR) mode. See “FET Driver” on page 136. In this mode a suitable voltage
drop is developed across the Charge FET to ensure proper operating voltage at the VFET pin.
This will ensure normal operation of the chip during 0-volt charging without setting the charger in
quick-charge mode before the cell has reached a safe cell voltage.
t
cΔv
I
AVG
----------- -
CREG
0.4V
⋅
I
AVG
------------------------------
---
==