Datasheet

118

8024A–AVR–04/08

ATmega8HVA/16HVA

Figure 21-1. Reference Circuitry

21.3 Register Description

21.3.1 BGCCR – Bandgap Calibration C Register

• Bit 7 - BGD: Bandgap Disable

Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared

(zero) before enabling CC-ADC, V-ADC or Battery Protection, and must remain unset (zero)

while either of these modules are enabled.

• Bit 6 – Res: Reserved Bit

This bit is reserved for future use.

• Bit 5:0 – BGCC5:0: BG Calibration of PTAT Current

These bits are used for trimming of the nominal value of the bandgap reference voltage. These

bits are binary coded. Minimum VREF: 000000, maximum VREF: 111111. Step size approxi-

mately 2 mV.

Updating the BGCC bits will affect both the regulator output voltage and the BOD detection

level. The BOD will react quickly to the new detection level, while the voltage regulator will adjust

the output voltage more slowly due to the external reservoir capacitor. Therefore, if the value is

increased more than a certain step size, the new BOD level may rise above the regulator output

voltage, and a false BOD reset will occur. It is recommended that the BGCC bits are updated

with a step size of 1. To allow the voltage regulator to reach the new level between each step, a

delay of 20 µs should be added between each update of the BGCC values .

BG Calibration

BG Reference

VREF

VREF_P

VREF_N

VREF_GND

CRE

VPTAT

1.1V

0.22V

Bit 7 6 5 4 3 2 1 0

(0xD0) BGD – BGCC5 BGCC4 BGCC3 BGCC2 BGCC1 BGCC0 BGCCR

Read/Write R/W R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0