Datasheet

116
8024A–AVR–04/08
ATmega8HVA/16HVA
20.4.4 DIDR0 – Digital Input Disable Register 0
• Bits 7:2 – Res: Reserved Bits
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when DIDR0 is written.
• Bit 1:0 – PA1DID:PA0DID: Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding Port A pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the PA1:0 pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
T
(K)
VADCH/L VPTAT CAL
⋅
16384
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=
Bit 765432 1 0
(0x7E) – – – – – – PA1DID PA0DID DIDR0
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0