Datasheet

114
8024A–AVR–04/08
ATmega8HVA/16HVA
20.4 Register Description
20.4.1 VADMUX – V-ADC Multiplexer Selection Register
• Bit 7:4 – RES: Reserved Bits
These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero.
• Bit 3:0 – VADMUX3:0: V-ADC Channel Selection Bits
The VADMUX bits determine the V-ADC channel selection. See Table 20-1 on page 114.
Note: 1. VTEMP must be measured in Active mode to get the highest accuracy when using calibration
value stored in signature row.
20.4.2 VADCSR – V-ADC Control and Status Register
• Bit 7:4 – RES: Reserved Bits
These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero.
• Bit 3 – VADEN: V-ADC Enable
Writing this bit to one enables V-ADC conversion. By writing it to zero, the V-ADC is turned off.
Turning the V-ADC off while a conversion is in progress will terminate this conversion. Note that
the bandgap voltage reference must be enabled separately, see “BGCCR – Bandgap Calibra-
tion C Register” on page 118.
• Bit 2 – VADSC: Voltage ADC Start Conversion
Write this bit to one to start a new conversion of the selected channel.
Bit 7654 3 2 1 0
(0x7C)
––––VADMUX3VADMUX2VADMUX1VADMUX0VADMUX
Read/Write R R R R R/W R/W R/W R/W
Initial Value0000 0 0 0 0
Table 20-1. VADMUX channel selection
VADMUX3:0 Channel Selected Scale
0000 RESERVED –
0001 CELL 1 0.2
0010 CELL 2 0.2
0011 RESERVED –
0100 VTEMP
(1)
1.0
0101 ADC0 1.0
0110 ADC1 1.0
0111...1111 RESERVED –
Bit 76543210
(0x7A)
–– – –
VADEN VADSC VADCCIF VADCCIE VADCSR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0