Datasheet

112
8024A–AVR–04/08
ATmega8HVA/16HVA
20. Voltage ADC – 5-channel General Purpose 12-bit Sigma-Delta ADC
20.1 Features
• 12-bit Resolution
• 519µs Conversion Time @ 1 MHz clk
VADC
• Two Differential Input Channels for Cell Voltage Measurements
• Three Single Ended Input Channels
• 0.2x Pre-scaling of Cell Voltages
• Interrupt on V-ADC Conversion Complete
20.2 Overview
The ATmega8HVA/16HVA features a 12-bit Sigma-Delta ADC.
The Voltage ADC (V-ADC) is connected to five different sources through the Input Multiplexer.
There are two differential channels for Cell Voltage measurements. These channels are scaled
0.2x to comply with the Full Scale range of the V-ADC. In addition there are three single ended
channels referenced to SGND. One channel is for measuring the internal temperature sensor
VPTAT and two channels for measuring the voltage at ADC0 and ADC1.
When the V-ADC is not used, power consumption can be minimized by writing the PRVADC bit
in PRR0 to one. See ”PRR0 – Power Reduction Register 0” on page 39 for details on how to use
the PRVADC bit.
Figure 20-1. Voltage ADC Block Schematic
20.3 Operation
To enable V-ADC conversions, the V-ADC Enable bit, VADEN, in V-ADC Control and Status
Register – VADCSR must be set. If this bit is cleared, the V-ADC will be switched off, and any
ongoing conversions will be terminated. The V-ADC is automatically disabled in Power-save and
V-ADC CONVERSION COMPLETE IRQ
8-BIT DATA BUS
V-ADC MULTIPLEXER
SEL. REG (VADMUX)
V-ADC CONTROL AND
STATUS REG (VADCSR)
V-ADC DATA REGISTER
(VADCL/ADCH)
VADCCIE
VADCCIF
12-BIT
SIGMA-DELTA ADC
INPUT
MUX
V-ADC CONTROL
ADC1
ADC0
V
TEMP
PV2
PV1
NV
Note:
The shaded signals are scaled by 0.2,
other signals are scaled by 1.0
VREF SGND