Datasheet

110
8024A–AVR–04/08
ATmega8HVA/16HVA
19.7.3 CADICH and CADICL - CC-ADC Instantaneous Current
When a CC-ADC Instantaneous Current conversion is complete, the result is found in these two
registers. CADIC[15:0] represents the converted result in 2's complement format. CADIC[12:0]
are the 13-bit ADC result (including sign), while CADIC[15:13] are the sign extension bits.
When CADICL is read, the CC-ADC Instantaneous Current register is not updated until CADCH
is read. Reading the registers in the sequence CADICL, CADICH will ensure that consistent val-
ues are read. When a conversion is completed, both registers must be read before the next
conversion is completed, otherwise data will be lost.
19.7.4 CADAC3, CADADC2, CADAC1, CADAC0 - CC-ADC Accumulate Current
The CADAC3, CADAC2, CADAC1 and CADAC0 Registers contain the Accumulate Current
measurements in 2's complement format. CADAC[17:0] are the 18-bit ADC result (including
sign), while CADAC[31:18] are the sign extension bits.
When CADAC0 is read, the CC-ADC Accumulate Current register is not updated until CADAC3
is read. Reading the registers in the sequence CADAC0, CADAC1, CADAC2, CADAC3 will
ensure that consistent values are read. When a conversion is completed, all four registers must
be read before the next conversion is completed, otherwise data will be lost.
Bit 151413121110 9 8
76543210
(0xE9) CADIC[15:8] CADICH
(0xE8) CADIC[7:0] CADICL
Read/Write RRRRRRRR
RRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
00000000
Bit 3130292827262524
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
76543210
(0xE3) CADAC[31:24] CADAC3
(0xE2) CADAC[23:16] CADAC2
(0xE1) CADAC[15:8] CADAC1
(0xE0) CADAC[7:0] CADAC0
Read/Write RRRRRRRR
RRRRRRRR
RRRRRRRR
Initial Value00000000
00000000
00000000