Datasheet

108
8024A–AVR–04/08
ATmega8HVA/16HVA
• Bit 5 - CADUB: CC-ADC Update Busy
The CC-ADC operates in a different clock domain than the CPU. Whenever a new value is writ-
ten to CADCSRA or CADRC this value must be synchronized to the CCADC clock domain.
Subsequent writes to these registers will be blocked during this synchronization. Synchroniza-
tion of one of the registers will block updating of all the others. The CADUB bit will be read as
one while any of these registers is being synchronized, and will be read as zero when neither
register is being synchronized.
• Bits 4:3: CADAS[1:0]: CC-ADC Accumulate Current Select
The CADAS bits select the conversion time for the Accumulate Current output as shown in Table
19-1.
Note: 1. The actual value depends on the actual frequency of the Slow RC oscillator, see
”Slow RC Oscillator” on page 26
.
• Bits 2:1: CADSI[1:0]: CC-ADC Current Sampling Interval
The CADSI bits determine the current sampling interval for the Regular Current detection as
shown in Table 19-2.
Notes: 1. The actual value depends on the actual frequency of the Slow RC oscillator, see ”Slow RC
Oscillator” on page 26
.
2. Sampling time ~ 12 ms.
• Bit 0 - CADSE: CC-ADC Sampling Enable
When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the
CCADC enters Regular Current detection mode.
Table 19-1. CC-ADC Accumulate Current Conversion Time
CADAS[1:0]
CC-ADC Accumulate Current
Conversion Time
(1)
Number of CC-ADC Clock
Cycles
00 125 ms 4096
01 250 ms 8192
10 500 ms 16384
11 1s 32768
Table 19-2. CC-ADC Regular Current Sampling Interval
CADSI[1:0]
CC-ADC Regular Current
Sampling Interval
(1)(2)
Number of CC-ADC Clock
Cycles
00 250 ms (+ sampling time) 8192 (+ sampling time)
01 500 ms (+ sampling time) 16384 (+ sampling time)
10 1s (+ sampling time) 32768 (+ sampling time)
11 2s (+ sampling time) 65536 (+ sampling time)