Datasheet

106
8024A–AVR–04/08
ATmega8HVA/16HVA
Figure 19-3. Accumulation Current Conversions
19.4 Regular Current Detection Operation
By setting the CADSE bit in CADCSRA the CC-ADC will enter a special Regular Current Detec-
tion Sampling Mode.
In this mode the CC-ADC will do one Instantaneous Current Conversion on regular sampling
intervals while updating of the Accumulation Current Register is automatically disabled. The
sampling interval is controlled by writing to the CADSI bits in CADCSRA.
Each time a conversion is completed the result is compared with Regular Charge/Discharge
Threshold levels specified in the CADRC register. If interrupt is enabled and the voltage is
above/below the specified limit a Regular Current Detection Interrupt will be issued. Figure 19-4
illustrates the Regular Current Detection Mode
Figure 19-4. Regular Current Detection Mode (CADSE=1)
The Regular Current Detection has a separate Interrupt and by setting the CADRCIE bit, this
interrupt is enabled. Note that this Regular Current Detection interrupt cannot wake-up the CPU
from sleep mode. To be able to use the Regular Current Detection function in sleep modes, the
Enable
Accumulation
Interrupt
Accumulation
Data
Read byte 1
Read byte 2
Read byte 3
Read byte 4
125, 250, 500,
or 1000 ms
125, 250, 500,
or 1000 ms
1, 2, 3, or 4s settling
250, 500,
1000, or 2000 ms
INVALID DATA DATA 1 DATA 2 DATA 3 DATA 4
Measure Turn-off
~12ms
~250, 500, 1000, 2000ms
Measure
~12ms
Turn-off
~250, 500, 1000, 2000ms
Regular Current
Detection Operation
Regular Current
Detection Interupt
Regular Charge
Current Threshold
Regular Discharge
Current Threshold
Current through R
SENSE