Features • High Performance, Low Power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • • • – 131 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 4 MIPS Throughput at 4 MHz High Endurance Non-volatile Memorie segments – 8K/16K Bytes of In-System Self-Programmable Flash Program Memory(ATmega8HVA/16HVA) – 256 Bytes EEPROM – 512 Bytes Internal SRAM – Write/Erase cycles: 10,000 Flash/100,000 EEPRO
1. Pin Configurations 1.1 LGA Figure 1-1. LGA - Pinout ATmega8HVA/16HVA 1 2 3 4 5 6 7 8 A B C D E Figure 1-2.
ATmega8HVA/16HVA 1.2 TSOP Figure 1-3. 1.3 1.3.1 TSOP - pinout ATmega8HVA/16HVA PV2 1 28 OD PV1 2 27 OC NV 3 26 GND GND 4 25 BATT VFET 5 24 PC0 (RXD/TXD/INT0) CF1P 6 23 VCC CF1N 7 22 GND CF2P 8 21 PB3 (MISO/INT2) CF2N 9 20 PB2 (MOSI/INT1) VREG 10 19 PB1 (SCK) VREF 11 18 PB0 (SS/CKOUT) VREFGND 12 17 PA2 (RESET/dW) PI 13 16 PA1 (ADC1/SGND/T1) NI 14 15 PA0 (ADC0/SGND/T0) Pin Descriptions VFET Input to the internal voltage regulator. 1.3.
1.3.7 GND Ground 1.3.8 Port A (PA1..PA0) Port A serves as a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega8HVA/16HVA 2. Overview The ATmega8HVA/16HVA is a monitoring and protection circuit for 1-cell and 2-cell Li-ion applications with focus on high security/authentication, accurate monitoring, low cost and high utilization of the cell energy. The device contains secure authentication features as well as autonomous battery protection during charging and discharging. The chip allows very accurate accumulated current measurements using an 18-bit ADC with a resolution of 0.84 µV.
The ATmega8HVA/16HVA contains a 12-bit ADC that can be used to measure the voltage of each cell individually. The ADC can also be used to monitor temperature, either on-chip temperature using the built-in temperature sensor, external temperature using thermistors connected to dedicated ADC inputs. The ATmega8HVA/16HVA contains a high-voltage tolerant, open-drain IO pin that supports serial communication. Programming can be done in-system using the 4 General Purpose IO ports that support SPI programming.
ATmega8HVA/16HVA 2.1 Comparison Between ATmega8HVA and ATmega16HVA The ATmega8HVA and ATmega16HVA differ only in memory size and interrupt vector size. Table 2-1 summarizes the different configuration for the two devices. Table 2-1. Configuration summary Device Flash Interrupt vector size ATmega8HVA 8K 1 Word ATmega16HVA 16K 2 Word 3.
7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1.
ATmega8HVA/16HVA ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
7.3.1 SREG – AVR Status Register Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
ATmega8HVA/16HVA 7.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
Figure 7-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.
ATmega8HVA/16HVA 7.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag.
ATmega8HVA/16HVA When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 7.7.
8. AVR Memories 8.1 Overview This section describes the different memories in the ATmega8HVA/16HVA. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8HVA/16HVA features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.2 In-System Reprogrammable Flash Program Memory The ATmega8HVA/16HVA contains 8K/16K bytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega8HVA/16HVA the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 768 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 512 locations address the internal data SRAM.
Figure 8-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 8.4 Next Instruction EEPROM Data Memory The ATmega8HVA/16HVA contains 256 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
ATmega8HVA/16HVA I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega8HVA/16HVA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
• Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations.
ATmega8HVA/16HVA EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. Caution: A BOD reset during EEPROM write will invalidate the result of the ongoing operation.
Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r17) in address register out EEAR, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
ATmega8HVA/16HVA Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r17) in address register out EEAR, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<
9. System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 34. The clock systems are detailed below. Figure 9-1.
ATmega8HVA/16HVA 9.1.5 Coulomb Counter ADC Clock - clkCCADC The Coulomb Counter ADC is provided with a dedicated clock domain. This allows operating the Coulomb Counter ADC in low power modes like Power-save for continuous current measurements. 9.1.6 Watchdog Timer and Battery Protection Clock The Watchdog Timer and Battery Protection are provided with a dedicated clock domain. This allows operation in all modes except Power-off.
9.4 Slow RC Oscillator The Slow RC Oscillator provides a 131 kHz clock (typical value, refer to section "Electrical Characteristics" on page 164 for details). This clock can be used as a timing reference for run-time calibration of the Fast RC Oscillator and for accurately determining the actual ULP Oscillator frequency, refer to ”OSI – Oscillator Sampling Interface” on page 28 for details. The Slow RC oscillator also provides the clock for the Coulomb Counter ADC.
ATmega8HVA/16HVA 9.7 Watchdog Timer, Battery Protection and Coulomb Counter ADC Clock The clock source for the Watchdog Timer, Battery Protection and Coulomb Counter ADC (CCADC) is the Ultra Low Power RC Oscillator. The Oscillator is automatically enabled in all operational modes. It is also enabled during reset. 9.8 Clock Startup Sequence When the CPU wakes up from Power-save, the CPU clock source is used to time the start-up, ensuring a stable clock before instruction execution starts.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, may be faster than the CPU's clock frequency. It is not possible to determine the state of the prescaler, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, two active clock edges are produced.
ATmega8HVA/16HVA Figure 9-2. Oscillator Sampling Interface Block Diagram Databus OSICSR Ultra Low Power RC Oscillator Slow RC Oscillator OSCILLATOR SELECT OSISEL0 Edge Detector 7 bit prescaler osi_posedge (1) Fast RC Oscillator Note: 1. One prescaled Slow RC/ULP oscillator period corresponds to 128 times the actual Slow RC/ULP oscillator period. The osi_posedge signal pulses on each rising edge of the prescaled Slow RC/ ULP oscillator clock.
being enabled by the OSI module. Hence, the calibration algorithm may use the time between the first and second osi_posedge as time reference for calculations. Another usage of OSI is determining the ULP frequency accurately. The ULP frequency at THOT and the ULP temperature coefficient are stored in the signature row, allowing the ULP frequency to be calculated directly.
ATmega8HVA/16HVA The FCAL[4:0] bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x1F gives the highest frequency in the range. Incrementing FCAL[4:0] by 1 will give a frequency increment of less than 1.5 % in the frequency range 7.3-8.1 MHz. With an accurate time reference, an oscillator accuracy of ±1% can be achieved after calibration.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, or clear the CLKPCE bit. • Bit 1:0 – CLKPS1:0: Clock Prescaler Select Bit 1..
ATmega8HVA/16HVA • Bit 4 - OSISEL0: Oscillator Sampling Interface Select 0 Table 9-5. OSISEL Bit Description OSISEL0 Oscillator source 0 ULP Oscillator 1 Slow RC Oscillator • Bit 1 – OSIST: Oscillator Sampling Interface Status This bit continuously displays the phase of the prescaled clock. This bit can be polled by the CPU to determine the rising and falling edges of the prescaled clock. • Bit 0 – OSIEN: Oscillator Sampling Interface Enable Setting this bit enables the Oscillator Sampling Interface.
10. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 10.1 Sleep Modes Figure 9-1 on page 24 presents the different clock systems in the ATmega8HVA/16HVA, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
ATmega8HVA/16HVA Figure 10-1. Sleep Mode State Diagram Reset From all States Except Power-on Reset RESET Reset Time-out Active Interrupt Sleep Sleep Interrupt Interrupt ADC NRM Sleep Sleep or Black-out Detection Idle Black-out Detection Power-save Black-out Detection Black-out Detection Power-off Charger Connected Table 10-2.
Table 10-2. Active modules in different Sleep Modes (Continued) Mode Active Idle ADC Noise Reduction Power-save X X X X X X X X CHARGER_DETECT X X X X VREGMON X X X OSI X X Module WDT VREG (1) Power-off X Notes: 1. Discharge FET must be switched off for Charger Detect to be enabled. 2. RCOSC_FAST runs in Power-save mode if DUVR mode is enabled. It also runs for approximately 125 ms after C-FET/DFET has been enabled. 3.
ATmega8HVA/16HVA Note that if a level triggered interrupt is used for wake-up from Power-save mode, the changed level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 56 for details. When waking up from Power-save mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined in ”Clock Sources” on page 25. 10.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VREG/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Register. Refer to ”DIDR0 – Digital Input Disable Register 0” on page 116 for details. 10.7.3 On-chip Debug System A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes.
ATmega8HVA/16HVA 10.8 10.8.1 Register Description SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero.
• Bit 3 - PRSPI: Power Reduction Serial Peripheral Interface Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be reinitialized to ensure proper operation. • Bit 2 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.
ATmega8HVA/16HVA 11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 11-1. Reset Logic DATA BUS PORF OCDRF VREG EXTRF WDRF BODRF MCU Status Register (MCUSR) Brown-out Detection Power-on Reset Circuit/ Charger Detect VFET BATT POR VREG Pull-up Resistor RESET /dW SPIKE FILTER Reset Circuit debugWIRE Watchdog Timer COUNTER RESET Ultra Low Power RC Oscillator Clock Generator Delay Counters TIMEOUT CK SUT[2:0] 11.2.
ATmega8HVA/16HVA Figure 11-2. Normal Start-up Sequence in Power-off. V POT 4 VFET DUVR VBATT 3 5 1 2 VREG Operating Mode Power-off RESET Active POR Reset Internal Reset 4/8/16/32/64/128/256/512 ms 1. The charger voltage pulls the BATT pin above the Power-on Threshold Voltage (VPOT). 2. When VBATT rises above VPOT, ATmega8HVA/16HVA turns on the Voltage Regulator and VREG starts to rise. The POR reset will go high while VREG is rising and initiate the internal reset state of the chip.
5. When the internal reset goes low, software starts up and loads the VREF calibration registers to get VREF = 1.100V. As the VREF voltage changes, VREG voltage and VFET DUVR voltage will rise proportionally to VREF. Now the chip can operate normally, but writing to EEPROM in DUVR mode for single cell applications should be avoided. 11.2.2 External Reset An External Reset is generated by a low level on the RESET pin.
ATmega8HVA/16HVA The BOD is automatically enabled in all modes of operation, except in Power-off mode. When the BOD is enabled, and VREG decreases to a value below the trigger level (VBOT- in Figure 11-5), the Brown-out Reset is immediately activated. When VREG increases above the trigger level (VBOT+ in Figure 11-5), the delay counter starts the MCU after the Time-out period tTOUT has expired. Figure 11-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET TIME-OUT tTOUT INTERNAL RESET 11.2.
11.3 11.3.1 Watchdog Timer Features • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16 ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 11.3.2 Overview ATmega8HVA/16HVA has an Enhanced Watchdog Timer (WDT). The WDT counts cycles of the Ultra Low Power RC Oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.
ATmega8HVA/16HVA 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the Watchdog Timer.
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.
ATmega8HVA/16HVA 11.4 11.4.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – OCDRF WDRF BODRF EXTRF PORF Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 MCUSR See Bit Description • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero.
• Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF.
ATmega8HVA/16HVA . Table 11-2. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out(1) 0 0 0 0 2K cycles 16 ms 0 0 0 1 4K cycles 32 ms 0 0 1 0 8K cycles 64 ms 0 0 1 1 16K cycles 0.13s 0 1 0 0 32K cycles 0.26s 0 1 0 1 64K cycles 0.51s 0 1 1 0 128K cycles 1.0s 0 1 1 1 256K cycles 2.0s 1 0 0 0 512K cycles 4.1s 1 0 0 1 1024K cycles 8.
12. Interrupts 12.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega8HVA/16HVA. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 13. 12.2 Interrupt Vectors in ATmega8HVA . Table 12-1. Vector No.
ATmega8HVA/16HVA Addres s 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0X000F 0x0010 0x0011 Label s Code Comments rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp RESET BPINT VREGMON_INT EXT_INT0 EXT_INT1 EXT_INT2 WDT TIM1_IC TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_IC TIM0_COMPA TIM0_COMPB TIM0_OVF SPI, STC VADC CCADC_CONV 0x0012 0x0013 rjmp rjmp CCADC_REC_CUR CCADC_ACC 0x0014 ; rjmp EE_RDY ldi r16,
12.3 Interrupt Vectors in ATmega16HVA . Table 12-2. Vector No.
ATmega8HVA/16HVA The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega16HVA is: Addres s 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0X001E 0x0020 0x0022 Label s Code Comments jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp RESET BPINT VREGMON_INT EXT_INT0 EXT_INT1 EXT_INT2 WDT TIM1_IC TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_IC TIM0_COMPA TIM0_COMPB TIM0_OVF SPI, STC VADC CCADC_C
13. External Interrupts 13.1 Overview The External Interrupts are triggered by the INT2:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Register – EICRA.
ATmega8HVA/16HVA Table 13-1. ISCn1 ISCn0 0 0 The low level of INTn generates an interrupt request. 0 1 Any logical change on INTn generates an interrupt request. 1 0 The falling edge of INTn generates an interrupt request. 1 1 The rising edge of INTn generates an interrupt request. Note: 13.2.2 Interrupt Sense Control Description 1. n = 2, 1, or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register.
14. High Voltage I/O Ports 14.1 Overview All high voltage AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the state of one port pin can be changed without unintentionally changing the state of any other pin with the SBI and CBI instructions. All high voltage I/O pins have protection Zener diodes to Ground as indicated in Figure 14-1. See ”Electrical Characteristics” on page 165 for a complete list of parameters. Figure 14-1.
ATmega8HVA/16HVA 14.2 High Voltage Ports as General Digital I/O 14.3 Overview The high voltage ports are high voltage tolerant open collector output ports. In addition they can be used as general digital inputs. Figure 14-2 shows a functional description of one output port pin, here generically called Pxn. Figure 14-2.
14.4 Alternate Port Functions The High Voltage I/O has alternate port functions in addition to being general digital I/O. Figure 14-3 shows how the port pin control signals from the simplified Figure 14-2 on page 59 can be overridden by alternate functions. Figure 14-3.
ATmega8HVA/16HVA Table 14-1. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PVOE Port Value Override Enable If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.
14.5 14.5.1 14.5.
ATmega8HVA/16HVA 15. Low Voltage I/O-Ports 15.1 Overview All low voltage AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 15.2 Low Voltage Ports as General Digital I/O The low voltage ports are bi-directional I/O ports with optional internal pull-ups. Figure 15-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 15-2.
ATmega8HVA/16HVA If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 15.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 15.2.
Figure 15-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega8HVA/16HVA Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
15.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega8HVA/16HVA Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin. Table 15-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 15-5 on page 68 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 15-2.
15.3.1 Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 15-3. Table 15-3.
ATmega8HVA/16HVA 15.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 15-5. Table 15-5.
Table 15-6. Overriding Signals for Alternate Functions in PB3..
ATmega8HVA/16HVA 15.4 15.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – – CKOE PUD – – – – Read/Write R R R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
16. Timer/Counter0 and Timer/Counter1 Prescalers 16.1 Overview Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.1.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
ATmega8HVA/16HVA 16.2 External Clock Source An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 16-2 shows a functional equivalent block diagram of the Tn synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O).
16.3 16.3.1 Register Description TCCRnB – Timer/Counter n Control Register B Bit 7 6 5 4 3 2 1 0 - - - - - CSn2 CSn1 CSn0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCRnB • Bits 2, 1, 0 – CSn2, CSn1, CSn0: Clock Select n, Bit 2, 1, and 0 The Clock Select n bits 2, 1, and 0 define the prescaling source of Timer n. Table 16-1.
ATmega8HVA/16HVA 17. Timer/Counter(T/C0,T/C1) 17.1 Features • • • • • 17.2 Clear Timer on Compare Match (Auto Reload) Input Capture unit Four Independent Interrupt Sources (TOVn, OCFnA, OCFnB, ICFn) 8-bit Mode with Two Independent Output Compare Units 16-bit Mode with One Independent Output Compare Unit Overview Timer/Counter n is a general purpose 8-/16-bit Timer/Counter module, with one/two Output Compare units and Input Capture functionality.
17.2.1 Registers The Timer/Counter Low Byte Register (TCNTnL) and Output Compare Registers (OCRnA and OCRnB) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in Figure 17-1 on page 77) signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure.
ATmega8HVA/16HVA 17.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 17-2 on page 79 shows a block diagram of the counter and its surroundings. Figure 17-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select TCNTn count Control Logic clkTn Edge Detector Tn ( From Prescaler ) top Signal description (internal signals): count Increment or decrement TCNTn by 1.
17.5 Modes of Operation The mode of operation is defined by the Timer/Counter Width (TCWn), Input Capture Enable (ICENn) and the Waveform Generation Mode (WGMn0)bits in ”TCCRnA – Timer/Counter n Control Register A” on page 90. Table 17-2 on page 80 shows the different Modes of Operation. Table 17-2.
ATmega8HVA/16HVA Figure 17-3. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn Period 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCFnA Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care.
17.5.5 8-bit Input Capture Mode The Timer/Counter can be used in a 8-bit Input Capture mode, see Table 17-2 on page 80 for bit settings. For full description, see ”Input Capture Unit” on page 82. 17.5.6 16-bit Input Capture Mode The Timer/Counter can also be used in a 16-bit Input Capture mode, see Table 17-2 on page 80 for bit settings. For full description, see ”Input Capture Unit” on page 82. 17.
ATmega8HVA/16HVA When a change of the logic level (an event) occurs on the Input Capture pin (ICPx), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into Input Capture Register. If enabled (TICIEn=1), the Input Capture Flag generates an Input Capture interrupt.
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the trigger edge change is not required. Table 17-3. ICS0 Source 0 ICP00: osi_posedge pin from OSI module(1) 1 ICP01: Port PC0 Note: 1. See ”OSI – Oscillator Sampling Interface” on page 28 for details. Table 17-4. ICS1 17.
ATmega8HVA/16HVA 17.7.1 Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNTnH/L Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnB/A to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. 17.7.
Figure 17-8. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx shows the setting of OCFnA and the clearing of TCNTn in CTC mode. Figure 17-9. Timer/Counter Timing Diagram, CTC mode, with Prescaler (fclk_I/O/8) clkPCK clkTn (clkPCK /8) TCNTn (CTC) TOP - 1 OCRnx TOP BOTTOM BOTTOM + 1 TOP OCFnx 17.
ATmega8HVA/16HVA The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnB/A registers. Assembly Code Example ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Example unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ...
The following code examples show how to do an atomic read of the TCNTn register contents. Reading any of the OCRn register can be done by using the same principle.
ATmega8HVA/16HVA The following code examples show how to do an atomic write of the TCNTnH/L register contents. Writing any of the OCRnB/A registers can be done by using the same principle.
17.10 Register Description 17.10.1 TCCRnA – Timer/Counter n Control Register A Bit 7 6 5 4 3 2 1 0 TCWn ICENn ICNCn ICESn ICSn – – WGMn0 Read/Write R/W R/W R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 TCCRnA • Bit 7– TCWn: Timer/Counter Width When this bit is written to one 16-bit mode is selected. The Timer/Counter width is set to 16-bits and the Output Compare Registers OCRnA and OCRnB are combined to form one 16-bit Output Compare Register.
ATmega8HVA/16HVA 17.10.2 TCNTnL – Timer/Counter n Register Low Byte Bit 7 6 5 4 3 2 1 0 TCNTnL[7:0] TCNTnL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register TCNTnL gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNTnL Register blocks (disables) the Compare Match on the following timer clock.
17.10.5 OCRnB – Timer/Counter n Output Compare Register B Bit 7 6 5 4 3 2 1 0 OCRnB[7:0] OCRnB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNTnL in 8-bit mode and TCNTnH in 16-bit mode). A match can be used to generate an Output Compare interrupt. In 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Register.
ATmega8HVA/16HVA 17.10.7 TIFRn – Timer/Counter n Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 - - - - ICFn OCFnB OCFnA TOVn Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFRn • Bits 3 – ICFn: Timer/Counter n Input Capture Flag This flag is set when a capture event occurs, according to the setting of ICENn, ICESn and ICSn bits in the TCCRnA Register. ICFn is automatically cleared when the Input Capture Interrupt Vector is executed.
18. SPI – Serial Peripheral Interface 18.1 Features • • • • • • • • 18.
ATmega8HVA/16HVA The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
Table 18-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See ”Alternate Functions of Port B” on page 71 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
ATmega8HVA/16HVA Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega8HVA/16HVA 18.3 18.3.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
Figure 18-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 18-4.
ATmega8HVA/16HVA 18.5 18.5.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 18-5. 18.5.
ATmega8HVA/16HVA 18.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
19. Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC 19.1 Features • Sampled System Coulomb Counter • Low Power Sigma-Delta ADC Optimized for Coulomb Counting • Instantaneous Current Output with 3.9 ms Conversion Time • • • • 19.
ATmega8HVA/16HVA of lower resolution. The Accumulate Current Output provides a highly accurate current measurement for Coulomb Counting. The CC-ADC also provides a special Regular Current detection mode. This allows ultra-low power operation in Power-save mode when small charge or discharge currents are flowing. For offset cancellation the polarity of the input signal could be switched run time. Using this feature correctly will remove the internal CC-ADC offset. See application note AVR352. 19.
Figure 19-3. Accumulation Current Conversions Enable 125, 250, 500, or 1000 ms 1, 2, 3, or 4s settling 125, 250, 500, or 1000 ms 250, 500, 1000, or 2000 ms Accumulation Interrupt Accumulation Data INVALID DATA DATA 1 DATA 2 DATA 3 DATA 4 Read byte 1 Read byte 2 Read byte 3 Read byte 4 19.4 Regular Current Detection Operation By setting the CADSE bit in CADCSRA the CC-ADC will enter a special Regular Current Detection Sampling Mode.
ATmega8HVA/16HVA Instantaneous Current Interrupt should be enabled as wake-up source by setting the CADICIE bit. The device will then wake-up from sleep after each single IC measurement. To check if Regular Current Detection has occurred the Regular Current Detection flag, CADRCIF, should be read. 19.5 Offset Canceling by Polarity Switching The CC-ADC offers Polarity Switching for internal offset canceling.
• Bit 5 - CADUB: CC-ADC Update Busy The CC-ADC operates in a different clock domain than the CPU. Whenever a new value is written to CADCSRA or CADRC this value must be synchronized to the CCADC clock domain. Subsequent writes to these registers will be blocked during this synchronization. Synchronization of one of the registers will block updating of all the others.
ATmega8HVA/16HVA 19.7.2 CADCSRB - CC-ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0xE5) – CADACIE CADRCIE CADICIE – CADACIF CADRCIF CADICIF Read/Write R R/W R R/W R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CADCSRB • Bits 7 - Res: Reserved This bit is reserved bit and will always read as zero.
19.7.3 CADICH and CADICL - CC-ADC Instantaneous Current Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (0xE9) CADIC[15:8] (0xE8) CADIC[7:0] Read/Write Initial Value CADICH CADICL R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When a CC-ADC Instantaneous Current conversion is complete, the result is found in these two registers. CADIC[15:0] represents the converted result in 2's complement format.
ATmega8HVA/16HVA 19.7.5 CADRC- CC-ADC Regular Current Bit 7 6 5 4 3 2 1 0 CADRC[7:0] (0xE6) CADRC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The CC-ADC Regular Current Register determines the threshold level for the Regular Current detection. When the result of a CC-ADC Instantaneous Current conversion has an absolute value greater than, or equal to, the Regular Current level, the CC-ADC Regular Current Interrupt Flag is set.
20. Voltage ADC – 5-channel General Purpose 12-bit Sigma-Delta ADC 20.1 Features • • • • • • 20.2 12-bit Resolution 519µs Conversion Time @ 1 MHz clkVADC Two Differential Input Channels for Cell Voltage Measurements Three Single Ended Input Channels 0.2x Pre-scaling of Cell Voltages Interrupt on V-ADC Conversion Complete Overview The ATmega8HVA/16HVA features a 12-bit Sigma-Delta ADC. The Voltage ADC (V-ADC) is connected to five different sources through the Input Multiplexer.
ATmega8HVA/16HVA Power-off mode. Note that the bandgap voltage reference must be enabled and disabled separately, see ”BGCCR – Bandgap Calibration C Register” on page 118. Figure 20-2. Voltage ADC Conversion Diagram Start Conversion Interrupt Conversion Result OLD DATA INVALID DATA VA L I D D ATA INVALID DATA To perform a V-ADC conversion, the analog input channel must first be selected by writing to the VADMUX register.
20.4 20.4.1 Register Description VADMUX – V-ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 (0x7C) – – – – VADMUX3 VADMUX2 VADMUX1 VADMUX0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 VADMUX • Bit 7:4 – RES: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA and will always read as zero. • Bit 3:0 – VADMUX3:0: V-ADC Channel Selection Bits The VADMUX bits determine the V-ADC channel selection. See Table 20-1 on page 114.
ATmega8HVA/16HVA VADSC will read as one as long as the conversion is not finished. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. VADSC will automatically be cleared when the VADEN bit is written to zero. • Bit 1 – VADCCIF: V-ADC Conversion Complete Interrupt Flag This bit is set when a V-ADC conversion completes and the data registers are updated. The VADC Conversion Complete Interrupt is executed if the VADCCIE bit and the I-bit in SREG are set.
⋅ VPTAT CALT(K) = VADCH/L -------------------------------------------------------------16384 20.4.4 DIDR0 – Digital Input Disable Register 0 Bit 7 6 5 4 3 2 1 0 (0x7E) – – – – – – PA1DID PA0DID Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR0 • Bits 7:2 – Res: Reserved Bits These bits are reserved for future use. To ensure compatibility with future devices, these bits must be written to zero when DIDR0 is written.
ATmega8HVA/16HVA 21. Voltage Reference and Temperature Sensor 21.1 Features • Accurate Voltage Reference of 1.100V • Internal Temperature Sensor • Possibility for Runtime Compensation of Temperature Drift in Both Voltage Reference and Onchip Oscillators • External Decoupling for Optimum Noise Performance • Low Power Consumption 21.2 Overview A low power band-gap reference provides ATmega8HVA/16HVA with an accurate On-chip voltage reference VREF of 1.100V.
Figure 21-1. Reference Circuitry 1.1V VREF BG Reference VREF_P VPTAT 0.22V CREF VREF_N BG Calibration Register 21.3 21.3.1 VREF_GND Register Description BGCCR – Bandgap Calibration C Register Bit 7 6 5 4 3 2 1 0 (0xD0) BGD – BGCC5 BGCC4 BGCC3 BGCC2 BGCC1 BGCC0 Read/Write R/W R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 BGCCR • Bit 7 - BGD: Bandgap Disable Setting the BGD bit to one will disable the bandgap voltage reference.
ATmega8HVA/16HVA 21.3.2 BGCRR – Bandgap Calibration R Register Bit 7 6 5 4 3 2 1 0 BGCR7 BGCR6 BGCR5 BGCR4 BGCR3 BGCR2 BGCR1 BGCR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 1 1 1 1 (0xD1) BGCRR • Bit 7:0 – BGCR7:0: BG Calibration of Resistor ladder These bits are used for temperature gradient adjustment of the bandgap reference. Figure 21-2 illustrates VREF as a function of temperature.
22. Voltage Regulator 22.1 Features • • • • 22.2 3.3V fixed output voltage Automatic selection of Step-up or Linear Regulation depending on VFET voltage. Fixed Linear Regulation mode can be selected for 2-cell applications Battery Pack Short mode allowing large voltage drop at VFET without pulling VREG low. Overview The Voltage Regulator is a Combined Step-up and Linear Voltage Regulator. This allows the same Voltage Regulator module to be used efficiently for a large range of input voltages.
ATmega8HVA/16HVA CF2P VIN VREF VREF CF2N VFET Voltage Regulator CF2 CF1P VIN CF1 CF1N Figure 22-1. Voltage regulator block diagram, combined Step-up and Linear mode VREF STEP-UP-REG VOUT CLK CLK CLK PV_CHECK VIN VREF ENABLE STEP_UP_EN LIN_EN VREG DCDC-CTRL STARTED STARTED ENABLE BATT DUALC_MODE ENABLE CHARGER DETECT CREG VIN VREF LIN-REG NFET DRIVER VOUT DUALC_MODE ENABLE Figure 22-2.
Figure 22-3. Voltage Regulator block diagram, Linear mode only CF2N VIN VREF VREF CF1P VFET Voltage Regulator CF2P VIN NC NC CF1N NC VREF STEP-UP-REG VOUT CLK CLK CLK PV_CHECK VIN VREF ENABLE STEP_UP_EN Disabled LIN_EN VREG DCDC-CTRL STARTED ENABLE BATT CHARGER DETECT STARTED DUALC_MODE CREG ENABLE VIN VREF LIN-REG NFET DRIVER VOUT DUALC_MODE ENABLE NC: No Connect Figure 22-4.
ATmega8HVA/16HVA 22.3 Voltage Regulator Monitor This module monitors the operating state of the Voltage Regulator. If the voltage at VFET drops below the Regulator Short-circuit Level (RSCL), see ”Electrical Characteristics” on page 165, the Voltage Regulator enters the Battery Pack Short mode. In this mode, VFET is disconnected from VREG to avoid a quick drop in the voltage regulator output.
23. Battery Protection 23.1 Features • • • • • • • 23.
ATmega8HVA/16HVA The Current Battery Protection (CBP) monitors the cell current by sampling the shunt resistor voltage at the PI/NI input pins. A differential operational amplifier amplifies the voltage with a suitable gain. The output from the operational amplifier is compared to an accurate, programmable On-chip voltage reference by an Analog Comparator.
When the Discharge High-current Protection is activated, the external D-FET and C-FET are disabled and a Current Protection Timer is started. This timer ensures that the FETs are disabled for at least one second. The application software must then set the DFE and CFE bits in the FET Control and Status Register to re-enable normal operation. If the D-FET is re-enabled while the loading of the battery still is too large, the Discharge High-current Protection will be activated again. 23.
ATmega8HVA/16HVA tection interrupt request to the CPU. This interrupt can wake up the CPU from any operation mode, except Power-off. The interrupt flags are cleared by writing a logic ‘1’ to their bit locations from the CPU. Note that there are neither flags nor status bits indicating that the chip has entered the Power Off mode. This is because the CPU is powered down in this mode.
• Bit 4 – SCD: Short Circuit Protection Disabled When the SCD bit is set, the Short-circuit Protection is disabled. The Short-circuit Detection will be disabled, and any Short-circuit condition will be ignored. • Bit 3 – DOCD: Discharge Over-current Protection Disabled When the DOCD bit is set, the Discharge Over-current Protection is disabled. The Discharge Over-current Detection will be disabled, and any Discharge Over-current condition will be ignored.
ATmega8HVA/16HVA Table 23-2. Short-circuit Protection Reaction Time. SCPT[6:0] with corresponding Short-circuit Delay Time. Short-circuit Protection Reaction Time(1) 23.9.4 ... ... 0x7E (7.83 - 7.88 ms) + Td(3) 0x7F (7.89 - 7.95 ms) + Td(3) Notes: 1. The actual value depends on the actual frequency of the ”Ultra Low Power RC Oscillator” on page 26. See ”Electrical Characteristics” on page 165. 2. Initial value: SCPT[0x10](1ms). 3.
applies when enabling the Discharge FET. For Charge Over-Current protection, this applies when enabling the Charge FET. With nominal ULP frequency this delay is maximum 0.1 ms. Note: 23.9.5 Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator cycles + 3 CPU clock cycles is required between each time the BPOCTR register is written. Any writing to the BPOCTR register during this period will be ignored.
ATmega8HVA/16HVA 23.9.6 BPSCD – Battery Protection Short-circuit Detection Level Register Bit 7 6 5 4 (0xF5) 3 2 1 0 SCDL[7:0] BPSCD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 0 0 1 1 • Bits 7:0 – SCDL7:0: Short-circuit Detection Level These bits sets the RSENSE voltage level for detection of Short-circuit in the discharge direction, as defined in Table 23-5 on page 132. Note: 23.9.
23.9.9 BPDHCD – Battery Protection Discharge-High-current Detection Level Register Bit 7 6 5 (0xF8) 4 3 2 1 0 DHCDL[7:0] BPDHCD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 0 0 1 1 • Bits 7:0 – DHCDL7:0: Discharge High-current Detection Level These bits sets the RSENSE voltage level for detection of Discharge High-current, as defined in Table 23-5 on page 132. Note: 23.9.
ATmega8HVA/16HVA Table 23-5. DL[7:0] with corresponding RSENSE Current for all Current Detection Levels (RSENSE = 10 mΩ, VREF = 1.100 ± 0.005V, TA = -10°C to 70°C) (Continued) Current Protection Detection Level 23.9.11 0xFE 7.5A 0xDD 8.0A 0xDE 8.5A 0xDF 9.0A 0xBD 9.5A 0xBE 10.0A 0x9D 11.0A 0x9E 12.0A 0x7C 13.0A 0x7D 14.0A 0x7E 15.0A 0x7F 16.0A 0x5C 17.0A 0x5D 18.0A 0x5E 19.
• Bit 0 - CHCIE : Charger High-current Protection Activated Interrupt The CHCIE bit enables interrupt caused by the Charge High-current Protection Activated Interrupt. 23.9.12 BPIFR – Battery Protection Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 (0xF3) - - - SCIF DOCIF COCIF DHCIF CHCIF Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 BPIFR • Bit 7:5 – Res: Reserved Bit These bits are reserved and will always read as zero.
ATmega8HVA/16HVA 24. FET Control 24.1 Overview The FET control is used to enable and disable the Charge FET and Discharge FET. Normally, the FETs are enabled and disabled by SW writing to the FET Control and Status Register (FCSR). However, the autonomous Battery Protection circuitry will if necessary override SW settings to protect the battery cells from too high Charge- or Discharge currents. Note that the CPU is never allowed to enable a FET that is disabled by the battery protection circuitry.
24.2 FET Driver 24.2.1 Features • Charge-pump for generating suitable gate drive for N-Channel FET switch on high side • Deep Under-voltage Recovery mode that allows normal operation while charging a Deeply Overdischarged battery from 0-volt 24.2.2 Overview The ATmega8HVA/16HVA includes a FET Driver. The FET Driver is designed for driving Nchannel FETs used as high side switch in 1- or 2-Cell Li-Ion battery pack. A block diagram of the FET driver is shown in Figure 24-2 on page 136.
ATmega8HVA/16HVA Figure 24-3. Switching NFET on and off during NORMAL operation 12.0 11.0 10.0 9.0 8.0 Voltage (V) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 100 24.3 Time (ms) 200 300 DUVR – Deep Under-Voltage Recovery Mode operation The purpose of DUVR mode is to control the Charge FET so that the VFET voltage is above the minimum operating voltage while charging cells below minimum operating voltage.
24.4 24.4.1 Register Description FCSR – FET Control and Status Register Bit 7 6 5 4 3 2 1 0 (0xF0) – – – – DUVRD CPS DFE CFE Read/Write R R R R R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 FCSR • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero.
ATmega8HVA/16HVA 25. debugWIRE On-chip Debug System 25.1 Features • • • • • • • • • • 25.
When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor is not required for debugWIRE functionality. • Connecting the RESET pin directly to VCC will not work. • Capacitors connected to the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 25.
ATmega8HVA/16HVA 26. Self-Programming the Flash 26.1 Overview The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
26.1.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • The CPU is halted during the Page Write operation. 26.2 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands.
ATmega8HVA/16HVA 26.2.1 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 26.2.2 Setting the Lock Bits from Software To set the Lock Bits, write the desired data to R0.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
ATmega8HVA/16HVA Table 26-1. Signature Row Addressing.
26.2.6 Programming Time for Flash when Using SPM The Fast RC Oscillator is used to time Flash accesses. Table 26-2 shows the typical programming time for Flash accesses from the CPU. Table 26-2. SPM Programming Time, fOSC = 8.0 MHz(1) Symbol Min Programming Time Max Programming Time Flash write (Page Erase, Page Write, and write Lock bits by SPM) 3.7 ms 4.5 ms Note: 1. Minimum and maximum programming times is per individual operation. Table 26-3.
ATmega8HVA/16HVA Table 26-4. Explanation of different variables used in Figure 26-1 and the mapping to the Zpointer, ATmega16HVA. Corresponding Z-value Variable PAGEMSB 26.3 26.3.1 Description Most significant bit which is used to address the words within one page (64 words in a page requires six bits PC [5:0]). 5 ZPCMSB Z13 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1. ZPAGEMSB Z6 Bit in Z-register that is mapped to PCMSB.
• Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.
ATmega8HVA/16HVA 27. Memory Programming 27.1 Program And Data Memory Lock Bits The ATmega8HVA/16HVA provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 27-1.
27.2.1 High Byte Table 27-3. Bit No Fuse High Byte Description 7:2 – – 1 OSCSEL1 Oscillator Select 1 0 (programmed) 0 OSCSEL0 Oscillator Select 0 1 (unprogrammed) Note: 27.2.2 Fuse High Byte Default Value 1 (unprogrammed) 1. The default OSCSEL1:0 setting should not be changed. OSCSEL1:0 = ‘00’ is reserved for test purposes. Other values are reserved for future use. Low Byte Table 27-4.
ATmega8HVA/16HVA 27.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both Programming mode, also when the device is locked. The three bytes reside in a separate address space. The signature bytes of ATmega8HVA/16HVA is given in Table 27-5. Table 27-5. Device ID Signature Bytes Address 27.
Figure 27-1. Serial Programming and Verify. +3.0 - 4.5V VCC MOSI MISO SCK RESET GND Table 27-8. Pin Mapping Serial Programming Symbol Pins I/O Description SCK PB1 I Serial Clock MOSI PB2 I Serial Data in MISO PB3 O Serial Data out When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction.
ATmega8HVA/16HVA 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time.
27.6.2 Serial Programming Instruction set Table 27-10 on page 154 and Figure 27-2 on page 155 describes the Instruction set. Table 27-10.
ATmega8HVA/16HVA If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 27-2 on page 155. Figure 27-2.
27.7 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATmega8HVA/16HVA. Figure 27-3. High-voltage Serial Programming +11.5 - 12.5V +3.0 - 3.5V RESET VCC SDI PB2 PB1 SDO Prog_enable[0] PB0 PB3 SII GND PC0 SCI Table 27-11.
ATmega8HVA/16HVA 27.8 High-voltage Serial Programming Algorithm To program and verify the ATmega8HVA/16HVA in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 27-14): 27.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in Serial (High-voltage) Programming mode: 1. Set Prog_enable pins listed in Table 27-12 on page 156 to “0000”, RESET pin to 0V and VCC to 0V. 2. Apply 3.0 - 3.5V between VCC and GND.
27.8.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. 1. Load command “Chip Erase” (see Table 27-14). 2. Wait after Instr.3 until SDO goes high for the “Chip Erase” cycle to finish. 3.
ATmega8HVA/16HVA Figure 27-5. High-voltage Serial Programming Waveforms SDI MSB LSB SII MSB LSB MSB SDO SCI 27.8.5 0 LSB 1 2 3 4 5 6 7 8 9 10 Programming the EEPROM The EEPROM is organized in pages, see ”High-voltage Serial Programming” on page 173. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 27-14 on page 160): 1.
Table 27-14. High-voltage Serial Programming Instruction Set for ATmega8HVA/16HVA Instruction Format Instruction Chip Erase Load “Write Flash” Command Load Flash Page Buffer Instr.1/5 Instr.2/6 Instr.
ATmega8HVA/16HVA Table 27-14. High-voltage Serial Programming Instruction Set for ATmega8HVA/16HVA (Continued) Instruction Format Instruction Read EEPROM Byte Instr.1/5 Instr.2/6 Instr.3 Instr.
28. Operating Circuit Figure 28-1. Operating Circuit Diagram, 2-cell. Rcf 1k RP OC PV2 470 Rbatt 1k Rdf 1k VFET OD + BATT + - BATT - BATT CP 0.1uF RP 470 PV1 CP 0.1uF RP NV 470 (MISO) PB3 (MOSI) PB2 SPI-communication (1) (SCK) PB1 Rpi PI 100 Rsense 0.010 (SS) PB0 ATmega8HVA/16HVA Ci 0.1uF Rni NI 100 PA1/ADC1/SGND Serial communication PC0 PA0/ADC0/SGND RT2 RT1 VREG VCC R1 10K CVCC 0.1 uF VREF VREFGND GND CREG 2.2 uF CF1N RESET CRESET 0.1 uF CREF 1 uF Notes: 162 1.
ATmega8HVA/16HVA Figure 28-2. Operating Circuit Diagram, 1-cell Rcf 1k RP OC PV2 Rbatt 1k Rdf 1k VFET OD + BATT + - BATT - BATT 470 RP 470 PV1 CP 0.1uF RP (MISO) PB3 NV 470 (MOSI) PB2 SPI-communication (1) (SCK) PB1 (SS) PB0 Rpi PI 100 Rsense 0.010 ATmega8HVA/16HVA Ci 0.1uF Rni Serial communication PC0 NI 100 VREG VCC PA1/ADC1/SGND CREG 2.2 uF CVCC 0.
Table 28-1. Recommended values for external devices Symbol Use Parameter Min Typ Max Unit R1 Pull-up resistor for thermistors R 8 10 12 kΩ RT1/RT2 NTC Thermistor R@25°C 8 10 12 kΩ 4000 N/A B-constant 3000 Source impedance when using PA1..PA0 as V-ADC inputs R 0 3 7 kΩ RS Worst-case Gain-error due to RS 0 1 2 % CREF VREF decoupling C 1 2.2 22 µF CREG VREG charge-storage capacitor C 1.1(1) 2.2 22 µF CVCC VCC decoupling capacitor C 0.
ATmega8HVA/16HVA 29. Electrical Characteristics 29.1 Absolute Maximum Ratings* Operating Temperature.................................... -20°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on PA0 - PA1, PI, and NI with respect to Ground ............................. -0.5V to VREG +0.5V Voltage on PB0 - PB3 with respect to Ground ............................. -0.5V to VCC +0.
29.2 DC Characteristics Table 29-1. Electrical Characteristics(1)(TA = -10°C to 70°C unless otherwise specified) Parameter Active Idle Supply Current ADC Noise Reduction Power-save Power-off 166 Condition Min Typ Max Unit 4.0 MHz, 4V ≤ VFET ≤ 8.4V, All PRR bits set. 2.5 mA 1.0 MHz, 4V ≤ VFET ≤ 8.4V, All PRR bits set. 800 μA 4.0 MHz, 4V ≤ VFET ≤ 8.4V, All PRR bits set. 550 μA 1.0 MHz, 4V ≤ VFET ≤ 8.4V, All PRR bits set. 270 μA 4.0 MHz, 4V ≤ VFET ≤ 8.
ATmega8HVA/16HVA Table 29-1. Electrical Characteristics(1)(TA = -10°C to 70°C unless otherwise specified) (Continued) Parameter Condition Min Voltage Regulator Operating Voltage Combined Step-up and Linear mode 1.8 9 Linear mode only 3.6 9 VFET = 1.8V, Iload = 2 mA 2.9 3.4 VFET = 2.0V, Iload = 5 mA 3.0 3.4 VFET = 2.4V, Iload = 8.5 mA 3.1 3.4 VFET = 3.0V, Iload = 10 mA 3.1 3.4 VFET = 3.8V, Iload = 10 mA 3.1 3.4 VFET = 5.5V, Iload = 10 mA 3.1 3.4 VFET = 9.0V, Iload = 10 mA 3.
Table 29-1. Electrical Characteristics(1)(TA = -10°C to 70°C unless otherwise specified) (Continued) Parameter Condition Min Reference Voltage Coulomb Counter Conversion Time and Resolution(5) Gain Error 26.9 µV Resolution 3.9 ms 0.84 µV Resolution 1000 ms -100 mV < VPI - NI < 100 mV VPTAT, Voltage Proportional to Absolute Temperature Absolute Accuracy(4) 4 LSB 2.5 ± 15 LSB ± 0.1 ±1 % 0.
ATmega8HVA/16HVA 29.4 General I/O Lines characteristics (1) Table 29-3. TA = -10°C to 70°C, VCC = 3.3V Symbol Parameter VIL Input Low Voltage, Except RESET pin VIL1 Input Low Voltage, RESET pin VIH Input High Voltage, Except RESET pin 0.6VCC(3) VCC + 0.5 V VIH1 Input High Voltage, RESET pin 0.9VCC(3) VCC + 0.5 V VOL Output Low Voltage IOL = 5mA 0.
29.5 FET Driver Characteristics Table 29-5. FET Driver Outputs specification(1)(TA = -10°C to 70°C unless otherwise specified) Parameter Condition VFET DC level (2) VFET ripple(2) Min. Typ. Max. Units 1 cell DUVR operation, VREF = 1.100V 1.9 2.0 2.1 V 2 cell DUVR operation, VREF = 1.100V 3.8 4.0 4.2 V 1 cell DUVR operation ±0.1 V 2 cell DUVR operation ±0.1 V 14.0 V OC, OD clamping voltage OC, OD Normal ON operation OC, OD VFET + 2.5 VFET + 4 VFET + 6.
ATmega8HVA/16HVA 29.7 SPI Timing Characteristics See Figure 29-1 on page 171 and Figure on page 172 for details. Table 29-7. SPI Timing Parameters Description Mode 1 SCK period Master See Figure 2 SCK high/low Master 50% duty 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 29.8 29.8.1 17 MSB ... LSB X Programming Characteristics Serial Programming Figure 29-2. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Figure 29-3.
ATmega8HVA/16HVA Table 29-8. Serial Programming Characteristics, TA = -10°C to 70°C, VCC = 3.0 - 5.5V (Unless Otherwise Noted) Symbol Parameter Min 1/tCLCL Oscillator Frequency (ATmega8HVA/16HVA) Typ Oscillator Period (ATmega8HVA/16HVA) tSHSL SCK Pulse Width High 2.2 tCLCL(1) tSLSH SCK Pulse Width Low 2.2 tCLCL(1) tOVSH MOSI Setup to SCK High tSHOX MOSI Hold after SCK High tSLIV SCK Low to MISO Valid 29.8.2 Units 4 MHz 0 tCLCL Note: Max 250 ns tCLCL 2 tCLCL 15 ns 1. 2.
30. Typical Characteristics – Preliminary Data All Typical Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These figures are preliminary and will be updated after characterization of actual silicon. These figures are not tested during manufacturing, and are added for illustration purpose only. Figure 30-1. Fast RC Oscillator frequency vs. OSCCAL value.
ATmega8HVA/16HVA 31.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBF) Reserved – – – – – – – – 176 Page (0xBE) Reserved – – – – – – – – (0xBD) Reserved – – – – – – – – (0xBC) Reserved – – – – – – – – (0xBB) Reserved – – – – – – – – (0xBA) Reserved – – – – – – – – (0xB9) Reserved – – – – – – – – (0xB8) Reserved – – – – – – – – (0xB7) Reserved – – – – – – – (0xB6) Reserved – – – – – – – – (0xB5) Reser
ATmega8HVA/16HVA Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7D) Reserved – – – – – – – – (0x7C) VADMUX – – – – (0x7B) Reserved – – – – – – – – (0x7A) VADCSR – – – – VADEN VADSC VADCCIF VADCCIE (0x79) VADCH – – – – (0x78) VADCL (0x77) Reserved – – – – – – – – (0x76) Reserved – – – – – – – – (0x75) Reserved – – – – – – – – (0x74) Reserved – – – – – – – – (0x73) Reserved – – – – – – – –
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1B (0x3B) Reserved – – – – – – – – Page 0x1A (0x3A) Reserved – – – – – – – – 0x19 (0x39) Reserved – – – – – – – – 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) OSICSR – – – OSISEL0 – – OSIST OSIEN 32 0x16 (0x36) TIFR1 – – – – ICF1 OCF1B OCF1A TOV1 93 0x15 (0x35) TIFR0 – – – – ICF0 OCF0B OCF0A TOV0 93 0x14 (0x34) Reserved – – – – – – – – 0x13 (0x33)
ATmega8HVA/16HVA 32.
32.
ATmega8HVA/16HVA 32. Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A Note: 1.
33. Ordering Information 33.1 ATmega8HVA Speed (MHz) Power Supply Ordering Code Package(1) Operation Range 1-4 1.8 - 9.0V ATmega8HVA-4CKU ATmega8HVA-4TU 36CK1 28T -20 to +85°C Notes: 1. Pb-free packaging, complies with the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 36CK1 36-pad, (6.50 x 3.50 x 0.85 mm Body, 0.60 mm Pitch), Land Grid Array (LGA) Package. 28T 28-lead (8 x 13.
ATmega8HVA/16HVA 33.2 ATmega16HVA Speed (MHz) Power Supply Ordering Code Package(1) Operation Range 1-4 1.8 - 9.0V ATmega16HVA-4CKU ATmega16HVA-4TU 36CK1 28T -20 to +85°C Notes: 1. Pb-free packaging, complies with the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 36CK1 36-pad, (6.50 x 3.50 x 0.85 mm Body, 0.60 mm Pitch), Land Grid Array (LGA) Package. 28T 28-lead (8 x 13.
34. Packaging Information 34.1 36CK1 D Marked A1 ID E A1 (Substrate) Top View A (Total PKG HGT) 0.08 Side View A1 BALL PAD CORNER 8 7 6 5 3 4 2 1 A COMMON DIMENSIONS (Unit of Measure = mm) B e C E e2 L1 e1 e Øb MIN NOM MAX D 6.40 6.50 6.60 E 3.40 3.50 3.60 A 0.59 0.66 0.73 A1 0.17 0.21 0.25 SYMBOL D b L L Bottom View Notes: 1. This drawing is for general information only. 2. Metal pad dimensions. 3. 0.70 REF L1 0.35 REF b 0.35 REF Øb NOTE 0.32 0.
ATmega8HVA/16HVA 34.2 28T PIN 1 0º ~ 5º c Pin 1 Identifier Area D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 D 13.20 13.40 13.60 D1 11.70 11.80 11.90 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.
35. Errata 35.1 35.1.1 ATmega8HVA Rev. A No known errata. 35.2 35.2.1 ATmega16HVA Rev. A No known errata.
ATmega8HVA/16HVA 36. Datasheet Revision History 36.1 Rev. 8024A – 04/08 1.
ATmega8HVA/16HVA 8024A–AVR–04/08
ATmega8HVA/16HVA Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1LGA ...........................................................................................................................2 1.2TSOP ....................................................................................................................
9.5Ultra Low Power RC Oscillator ................................................................................26 9.6CPU, I/O, Flash, and Voltage ADC Clock ................................................................26 9.7Watchdog Timer, Battery Protection and Coulomb Counter ADC Clock .................27 9.8Clock Startup Sequence ..........................................................................................27 9.9Clock Output ................................................................
ATmega8HVA/16HVA 14.4Alternate Port Functions ........................................................................................60 14.5Register Description ..............................................................................................62 15 Low Voltage I/O-Ports ............................................................................ 63 15.1Overview ................................................................................................................63 15.
19.6Configuration and Usage .....................................................................................107 19.7Register Description ............................................................................................107 20 Voltage ADC – 5-channel General Purpose 12-bit Sigma-Delta ADC 112 20.1Features ..............................................................................................................112 20.2Overview ...............................................................
ATmega8HVA/16HVA 25.3Physical Interface ................................................................................................139 25.4Software Break Points .........................................................................................140 25.5Limitations of debugWIRE ...................................................................................140 25.6Register Description ............................................................................................
34 Packaging Information ........................................................................ 184 34.136CK1 ..................................................................................................................184 34.228T ......................................................................................................................185 35 Errata ..................................................................................................... 186 35.1ATmega8HVA ....................
ATmega8HVA/16HVA vii 8024A–AVR–04/08
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