Datasheet

v
8018O–AVR–10/09
ATmega169P
22.6Changing Channel or Reference Selection .........................................................221
22.7ADC Noise Canceler ...........................................................................................222
22.8ADC Conversion Result ......................................................................................227
22.9ADC Register Description ...................................................................................229
23 LCD Controller ..................................................................................... 234
23.1Features ..............................................................................................................234
23.2Overview .............................................................................................................234
23.3Mode of Operation ...............................................................................................237
23.4LCD Usage ..........................................................................................................242
23.5LCD Register Description ....................................................................................246
24 JTAG Interface and On-chip Debug System ..................................... 252
24.1Overview .............................................................................................................252
24.2TAP – Test Access Port ......................................................................................253
24.3TAP Controller .....................................................................................................255
24.4Using the Boundary-scan Chain ..........................................................................256
24.5Using the On-chip Debug System .......................................................................256
24.6On-chip Debug Specific JTAG Instructions .........................................................257
24.7On-chip Debug Related Register in I/O Memory .................................................258
24.8Using the JTAG Programming Capabilities .........................................................258
24.9Bibliography .........................................................................................................258
25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 259
25.1Features ..............................................................................................................259
25.2System Overview ................................................................................................259
25.3Data Registers .....................................................................................................260
25.4Boundary-scan Specific JTAG Instructions .........................................................261
25.5Boundary-scan Chain ..........................................................................................262
25.6Boundary-scan Order ..........................................................................................272
25.7Boundary-scan Description Language Files ........................................................278
25.8Boundary-scan Related Register in I/O Memory .................................................279
26 Boot Loader Support – Read-While-Write Self-Programming ......... 280
26.1Features ..............................................................................................................280
26.2Overview .............................................................................................................280
26.3Application and Boot Loader Flash Sections .......................................................280
26.4Read-While-Write and No Read-While-Write Flash Sections ..............................281
26.5Boot Loader Lock Bits .........................................................................................284