Datasheet

264
8018P–AVR–08/10
ATmega169P
Figure 25-4. General Port Pin Schematic Diagram
CLK
RPx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
WPx: WRITE PINx REGISTER
PUD: PULLUP DISABLE
CLK : I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
Q
Q
D
Q
Q
D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
I/O
See Boundary-scan
Description for Details!
PUExn
OCxn
ODxn
IDxn
PUExn: PULLUP ENABLE for pin Pxn
OCxn: OUTPUT CONTROL for pin Pxn
ODxn: OUTPUT DATA to pin Pxn
IDxn: INPUT DATA from pin Pxn
RPx: READ PORTx PIN
RRx
RESET
Q
Q
D
CLR
PORTxn
WPx
0
1
WRx