Datasheet

22
8018P–AVR–08/10
ATmega169P
7.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU
cycles as described in Figure 7-3.
Figure 7-3. On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction