Datasheet

197
8018P–AVR–08/10
ATmega169P
Receiver will generate a parity value for the incoming data and compare it to the UPM0n setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
• Bit 2:1 – UCSZn[1:0]: Character Size
The UCSZn[1:0] bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 19-9. UPM Bits Settings
UPMn1 UPMn0 Parity Mode
00Disabled
01Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Table 19-10. USBSn Bit Settings
USBSn Stop Bit(s)
01-bit
12-bit
Table 19-11. UCSZ Bits Settings
UCSZn2 UCSZn1 UCSZn0 Character Size
0 0 0 5-bit
0 0 1 6-bit
0 1 0 7-bit
0 1 1 8-bit
100Reserved
101Reserved
110Reserved
1 1 1 9-bit
Table 19-12. UCPOLn Bit Settings
UCPOLn
Transmitted Data Changed
(Output of TxD Pin)
Received Data Sampled (Input on RxD
Pin)
0 Rising XCK Edge Falling XCK Edge
1 Falling XCK Edge Rising XCK Edge