Datasheet

106
8018P–AVR–08/10
ATmega169P
15. 16-bit Timer/Counter1
15.1 Features
• True 16-bit Design (that is, allows 16-bit PWM)
• Two independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
15.2 Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. Most register and bit references in this sec-
tion are written in general form. A lower case “n” replaces the Timer/Counter number, and a
lower case “x” replaces the Output Compare unit number. However, when using the register or
bit defines in a program, the precise form must be used, that is, TCNT1 for accessing
Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 15-1 on page 107. For
the actual placement of I/O pins, refer to Figure 1-1 on page 2. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the Section 15.11 ”16-bit Timer/Counter Register Description” on page 128.
The PRTIM1 bit in Section 9.9.2 ”PRR – Power Reduction Register” on page 45 must be written
to zero to enable Timer/Counter1 module.