Datasheet
Table Of Contents
- 1. Pin Configurations
- 2. Overview
- 2.1 Block Diagram
- 2.2 Comparison Between ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
- 2.3 Pin Descriptions
- 2.3.1 VCC
- 2.3.2 GND
- 2.3.3 Port A (PA7...PA0)
- 2.3.4 Port B (PB7...PB0)
- 2.3.5 Port C (PC7...PC0)
- 2.3.6 Port D (PD7...PD0)
- 2.3.7 Port E (PE7...PE0)
- 2.3.8 Port F (PF7...PF0)
- 2.3.9 Port G (PG5...PG0)
- 2.3.10 Port H (PH7...PH0)
- 2.3.11 Port J (PJ6...PJ0)
- 2.3.12 RESET
- 2.3.13 XTAL1
- 2.3.14 XTAL2
- 2.3.15 AVCC
- 2.3.16 AREF
- 2.3.17 LCDCAP
- 3. Resources
- 4. Data Retention
- 5. About Code Examples
- 6. Capacitive touch sensing
- 7. Register Summary
- 8. Instruction Set Summary
- 9. Ordering Information
- 10. Packaging Information
- 11. Errata
- 12. Datasheet Revision History

9
8284CS–AVR–6/11
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
Port D also serves the functions of various special features of the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page
79.
2.3.7 Port E (PE7...PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page
81.
2.3.8 Port F (PF7...PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.3.9 Port G (PG5...PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features of the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page
85.
2.3.10 Port H (PH7...PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port H output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port H also serves the functions of various special features of the ATmega3290PA/6490P as
listed on page 87.
2.3.11 Port J (PJ6...PJ0)
Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port J output buffers have symmetrical drive characteristics with both high sink and source capa-