Datasheet

311
8018P–AVR–08/10
ATmega169P
27.8.1 Serial Programming Pin Mapping
Figure 27-10. Serial Programming and Verify
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Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. V
CC
- 0.3V < AVCC < V
CC
+ 0.3V, however, AVCC should always be within 1.8V - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
>= 12 MHz
High: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
>= 12 MHz
27.8.2 Serial Programming Algorithm
When writing serial data to the ATmega169P, data is clocked on the rising edge of SCK.
When reading data from the ATmega169P, data is clocked on the falling edge of SCK. See Fig-
ure 27-11 on page 313 for timing details.
To program and verify the ATmega169P in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in Table 27-16 on page 314):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
Table 27-14. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PB2 I Serial Data in
MISO PB3 O Serial Data out
SCK PB1 I Serial Clock
VCC
GND
XTAL1
SCK
MISO
MOSI
RESET
+1.8V - 5.5V
AVCC
+1.8V - 5.5V
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