Datasheet

272
8018P–AVR–08/10
ATmega169P
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
hold,max
25.6 Boundary-scan Order
Table 25-5 shows the Scan order between TDI and TDO when the Boundary-scan chain is
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in
the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the
analog circuits, which constitute the most significant bits of the scan chain regardless of which
physical pin they are connected to. In Figure 25-3 on page 263, PXn. Data corresponds to FF0,
PXn. Control corresponds to FF1, and PXn. Pull-up_enable corresponds to FF2. Bit 4, bit 5, bit
6, and bit 7 of Port F is not in the scan chain, since these pins constitute the TAP pins when the
JTAG is enabled.
Table 25-4. Algorithm for Using the ADC
Step Actions ADCEN DAC MUXEN HOLD PRECH
PA3.
Data
PA3.
Control
PA3.
Pull-up_
Enable
1
SAMPLE_P
RELOAD
1 0x200 0x08 1 1 0 0 0
2 EXTEST
1 0x200 0x08 0 1 0 0 0
3
1 0x200 0x08 1 1 0 0 0
4
1 0x123 0x08 1 1 0 0 0
5
1 0x123 0x08 1 0 0 0 0
6
Verify the
COMP bit
scanned out
to be 0
1 0x200 0x08 1 1 0 0 0
7
1 0x200 0x08 0 1 0 0 0
8
1 0x200 0x08 1 1 0 0 0
9
1 0x143 0x08 1 1 0 0 0
10
1 0x143 0x08 1 0 0 0 0
11
Verify the
COMP bit
scanned out
to be 1
1 0x200 0x08 1 1 0 0 0
Table 25-5. ATmega169P Boundary-scan Order
Bit Number Signal Name Module
197 AC_IDLE
Comparator
196 ACO
195 ACME
194 AINBG