Datasheet

250
8018P–AVR–08/10
ATmega169P
23.5.4 LCDCCR – LCD Contrast Control Register
• Bits 7:5 – LCDDC2:0: LDC Display Configuration
The LCDDC2:0 bits determine the amount of time the LCD drivers are turned on for each volt-
age transition on segment and common pins. A short drive time will lead to lower power
consumption, but displays with high internal resistance may need longer drive time to achieve
satisfactory contrast. Note that the drive time will never be longer than one half prescaled LCD
clock period, even if the selected drive time is longer. When using static bias or blanking, drive
time will always be one half prescaled LCD clock period.
• Bit 4 – LCDMDT: LCD Maximum Drive Time
Writing this bit to one turns the LCD drivers on 100% on the time, regardless of the drive time
configured by LCDDC2:0.
• Bits 3:0 – LCDCC3:0: LCD Contrast Control
The LCDCC3:0 bits determine the maximum voltage V
LCD
on segment and common pins. The
different selections are shown in Table 23-8 on page 251. New values take effect every begin-
ning of a new frame.
Bit 76543210
(0xE7)
LCDDC2 LCDDC1 LCDDC0 LCDMDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 LCDCCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 23-7. LCD Display Configuration
LCDDC2 LCDDC1 LCDDC0 Nominal drive time
0 0 0 300 µs
00170 µs
0 1 0 150 µs
0 1 1 450 µs
1 0 0 575 µs
1 0 1 850 µs
1 1 0 1150 µs
11150% of clk
LCD_PS