Datasheet

235
8018P–AVR–08/10
ATmega169P
Figure 23-1. LCD Module Block Diagram
23.2.2 LCD Clock Sources
The LCD Controller can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
LCD
is by default equal to the system clock, clk
I/O
. When the
LCDCS bit in the LCDCRB Register is written to logic one, the clock source is taken from the
TOSC1 pin.
The clock source must be stable to obtain accurate LCD timing and hence minimize DC voltage
offset across LCD segments.
23.2.3 LCD Prescaler
The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The LCDPS2:0 bits
selects clk
LCD
divided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.
If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock further by
1 to 8.
Output from the clock divider clk
LCD_PS
is used as clock source for the LCD timing.
23.2.4 LCD Memory
The display memory is available through I/O Registers grouped for each common terminal.
When a bit in the display memory is written to one, the corresponding segment is energized (on),
and non-energized when a bit in the display memory is written to zero.
Clock
Multiplexer
12-bit Prescaler
0
1
Divide by 1 to 8
LCD
Timing
LCDCRB
LCDFRR
clk
i/o
TOSC
LCDCRA
D
A
T
A
B
U
S
clk
LCD
/4096
clk
LCD
/2048
clk
LCD
/128
clk
LCD
/1024
clk
LCD
/512
clk
LCD
/256
clk
LCD
/64
clk
LCD
/16
Analog
Switch
Array
lcdcs
lcdcd2:0
lcdps2:0
clk
LCD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
COM0
COM1
COM2
COM3
LCD Buffer/
Driver
V
LCD
LCDDR 18 -15
LCDDR 13 -10
LCDDR 8 - 5
LCDDR 3 - 0
LATCH
array
LCD Ouput
Decoder
LCDCCR
lcdcc3:0
Contrast Controller/
Power Supply
clk
LCD_PS
LCD
CAP
25 x
4:1
MUX
LCD_voltage_ok
2/3 V
LCD
1/2 V
LCD
1/3 V
LCD
Display
Configuration