Datasheet

103
8018P–AVR–08/10
ATmega169P
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting. Table 14-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits
are set to a normal or CTC mode (non-PWM).
Table 14-4 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on
page 97 for more details.
Table 14-5 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-
rect PWM mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on
page 99 for more details.
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 14-3. Compare Output Mode, non-PWM Mode
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 Toggle OC0A on compare match
1 0 Clear OC0A on compare match
1 1 Set OC0A on compare match
Table 14-4. Compare Output Mode, Fast PWM Mode
(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
01Reserved
10
Clear OC0A on compare match, set OC0A at BOTTOM
(non-inverting mode)
11
Set OC0A on compare match, clear OC0A at BOTTOM
(inverting mode)
Table 14-5. Compare Output Mode, Phase Correct PWM Mode
(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
01Reserved
10
Clear OC0A on compare match when up-counting. Set OC0A on
compare match when down counting.
11
Set OC0A on compare match when up-counting. Clear OC0A on
compare match when down counting.