Datasheet

266
8018P–AVR–08/10
ATmega169P
Table 25-1 summaries the scan registers for the external clock pin XTAL1, oscillators with
XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.
Notes: 1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided.
25.5.4 Scanning the Analog Comparator
The relevant Comparator signals regarding Boundary-scan are shown in Figure 25-7. The
Boundary-scan cell from Figure 25-8 on page 267 is attached to each of these signals. The sig-
nals are described in Table 25-2 on page 267.
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Figure 25-7. Analog Comparator
Table 25-1. Scan Signals for the Oscillator
(1)(2)(3)
Enable Signal
Scanned
Clock Line Clock Option
Scanned Clock Line
when not Used
EXTCLKEN EXTCLK (XTAL1) External Clock 0
OSCON OSCCK
External Crystal
External Ceramic Resonator
1
OSC32EN OSC32CK Low Freq. External Crystal 1
ACBG
BANDGAP
REFERENCE
ADC MULTIPLEXER
OUTPUT
ACME
AC_IDLE
ACO
ADCEN
ACD