Datasheet

248
8018P–AVR–08/10
ATmega169P
23.5.3 LCDFRR – LCD Frame Rate Register
• Bit 7 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 6:4 – LCDPS2:0: LCD Prescaler Select
The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further
divided by setting the clock divide bits (LCDCD2:0). The different selections are shown in Table
23-4. Together they determine the prescaled LCD clock (clk
LCD_PS
), which is clocking the LCD
module.
1 0 0 SEG0:20 21
1 0 1 SEG0:22 23
1 1 0 SEG0:23 24
1 1 1 SEG0:24 25
Table 23-3. LCD Port Mask (Continued)
LCDPM2 LCDPM1 LCDPM0
I/O Port in Use as Segment
Driver
Maximum Number of
Segments
Bit 76543210
(0xE6)
– LCDPS2 LCDPS1 LCDPS0 – LCDCD2 LCDCD1 LCDCD0 LCDFRR
Read/Write R R/W R/W R/W R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 23-4. LCD Prescaler Select
LCDPS2 LCDPS1 LCDPS0
Output from
Prescaler
clk
LCD
/N
Applied Prescaled LCD Clock Frequency
when LCDCD2:0 = 0, Duty = 1/4, and
Frame Rate = 64Hz
000clk
LCD
/16 8.1 kHz
001clk
LCD
/64 33 kHz
010clk
LCD
/128 66 kHz
011clk
LCD
/256 130 kHz
100clk
LCD
/512 260 kHz
101clk
LCD
/1024 520 kHz
110clk
LCD
/2048 1 MHz
111clk
LCD
/4096 2 MHz