Datasheet

158

8018P–AVR–08/10

ATmega169P

18. SPI – Serial Peripheral Interface

18.1 Features

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

18.2 Overview

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega169P and peripheral devices or between several AVR devices.

The PRSPI bit in ”PRR – Power Reduction Register” on page 45 must be written to zero to

enable SPI module.

Figure 18-1. SPI Block Diagram

(1)

Note: 1. Refer to Figure 1-1 on page 2, and Table 13-6 on page 74 for SPI pin placement.

SPI2X

DIVIDER

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