Features • High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 16 Kbytes of In-System Self-programmable Flash program memory – 512 Bytes EEPROM – 1 Kbytes Internal SRAM – Write/Erase cycles: 10,000 Flash/100
ATmega169P 1. Pin Configurations Pinout - TQFP/QFN/MLF LCDCAP 1 (RXD/PCINT0) PE0 2 GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (COM0) PA1 (COM1) PA2 (COM2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 64A (TQFP) and 64M1 (QFN/MLF) Pinout ATmega169P AVCC Figure 1-1. 64 1.
ATmega169P Pinout - DRQFN 64MC (DRQFN) Pinout ATmega169P A25 A23 B20 A4 A22 B4 B19 A21 B5 B18 A5 A6 A7 B7 Table 1-1.
ATmega169P 2. Overview The ATmega169P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Block Diagram PF0 - PF7 PA0 - PA7 XTAL2 Figure 2-1. XTAL1 2.1 PC0 - PC7 VCC GND PORTA DRIVERS PORTF DRIVERS DATA DIR. REG.
ATmega169P The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega169P 2.2 2.2.1 Pin Descriptions VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 Port A (PA7:PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated.
ATmega169P 2.2.7 Port E (PE7:PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega169P 2.2.14 AREF This is the analog reference pin for the A/D Converter. 2.2.15 LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Figure 23-2 on page 236. This capacitor acts as a reservoir for LCD power (V LCD ). A large capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target value.
ATmega169P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
ATmega169P 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation.
ATmega169P 6. AVR CPU Core 6.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 6.2 Architectural Overview Figure 6-1.
ATmega169P The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATmega169P 6.4 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.
ATmega169P 6.4.1 SPH and SPL – Stack Pointer Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) – – – – – SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write Initial Value 6.5 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Instruction Execution Timing This section describes the general access timing concepts for instruction execution.
ATmega169P 6.6 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
ATmega169P Assembly Code Example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<
ATmega169P 6.7 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
ATmega169P • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 6.8 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega169P 6.8.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-5. Figure 6-5.
ATmega169P 7. AVR Memories This section describes the different memories in the ATmega169P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega169P features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 7.1 In-System Reprogrammable Flash Program Memory The ATmega169P contains 16 Kbytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega169P 7.2 SRAM Data Memory Figure 7-2 shows how the ATmega169P SRAM Memory is organized. The ATmega169P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega169P 7.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 7-3. Figure 7-3.
ATmega169P 7.3 EEPROM Data Memory The ATmega169P contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. This section describes the access between the EEPROM and the CPU, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
ATmega169P When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
ATmega169P The following code examples show one assembly and one C function for writing to the EEPROM. To avoid that interrupts will occur during execution of these functions, the examples assume that interrupts are controlled (for example by disabling interrupts globally). The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
ATmega169P The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega169P 7.3.2 EEPROM Write During Power-down Sleep Mode When entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation is completed, the clock continues running, and as a consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down. 7.3.
ATmega169P 7.5 General Purpose I/O Registers The ATmega169P contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bitaccessible using the SBI, CBI, SBIS, and SBIC instructions. 7.5.1 GPIOR2 – General Purpose I/O Register 2 Bit 7.5.2 7.6.
ATmega169P 7.6.2 EEDR – EEPROM Data Register Bit 7 6 5 4 3 2 1 0 0x20 (0x40) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EEDR • Bits 7:0 – EEDR7:0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 7.6.
ATmega169P 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 40. The clock systems are detailed below. Figure 8-1.
ATmega169P 8.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. It also allows the LCD controller output to continue while the rest of the device is in sleep mode. 8.1.
ATmega169P 8.3 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel programmer. 8.4 Calibrated Internal RC Oscillator B default, the Internal RC Oscillator provides an approximate 8 MHz clock.
ATmega169P 8.5 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 8-2. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.
ATmega169P The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 8-6. Table 8-6. CKSEL0 SUT1:0 Start-up Time from Power-down and Power-save 0 00 258 CK(1) 14CK + 4.1 ms Ceramic resonator, fast rising power 0 01 258 CK(1) 14CK + 65 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) 14CK Ceramic resonator, BOD enabled 0 11 1K CK(2) 14CK + 4.
ATmega169P Table 8-8. Capacitance for Low-Frequency Crystal Oscillator Device 32 kHz Osc. Type Cap (Xtal1/Tosc1) Cap (Xtal2/Tosc2) System Osc. 16 pF 6 pF Timer Osc. 16 pF 6 pF ATmega169P The capacitance (Ce + Ci) needed at each TOSC pin can be calculated by using: Ce + Ci = 2 ⋅ CL – C s where Ce - is optional external capacitors as described in Figure 8-2 on page 33. Ci - is is the pin capacitance in Table 8-8. CL - is the load capacitance for a 32.
ATmega169P 8.7 External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 8-3. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 8-3. External Clock Drive Configuration NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 8-12. Table 8-11. Crystal Oscillator Clock Frequency CKSEL3..
ATmega169P 8.8 Timer/Counter Oscillator ATmega169P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator. See ”Low-frequency Crystal Oscillator” on page 34 for details on the oscillator and crystal requirements. ATmega169P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency.
ATmega169P 8.11 8.11.1 Register Description OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
ATmega169P “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting.
ATmega169P 9. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 9.1 Sleep Modes Figure 8-1 on page 30 presents the different clock systems in the ATmega169P, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
ATmega169P 9.2 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
ATmega169P 9.5 Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Powersave mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 and/or the LCD controller are enabled, they will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set.
ATmega169P 9.8 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 9.8.
ATmega169P 9.8.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled.
ATmega169P 9.9 9.9.1 Register Description SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 9-2. Table 9-2.
ATmega169P • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.
ATmega169P 10. System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega169P Figure 10-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 10.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and Reset Characteristics” on page 333.
ATmega169P Figure 10-3. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET 10.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”System and Reset Characteristics” on page 333) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
ATmega169P 10.2.3 Brown-out Detection ATmega169P has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
ATmega169P 10.3 Internal Voltage Reference ATmega169P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in ”System and Reset Characteristics” on page 333. To save power, the reference is not always turned on.
ATmega169P Figure 10-7. Watchdog Timer WATCHDOG OSCILLATOR 10.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 10.4.1.1 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction.
ATmega169P Assembly Code Example(1) WDT_off: ; Reset WDT wdr ; Write logical one to WDCE and WDE in r16, WDTCR ori r16, (1<
ATmega169P 10.5 10.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – – – JTRF WDRF BORF EXTRF PORF Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 MCUSR See Bit Description • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
ATmega169P • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2.
ATmega169P 11. Interrupts This section describes the specifics of the interrupt handling as performed in ATmega169P. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 15. 11.1 Interrupt Vectors in ATmega169P Table 11-1. Reset and Interrupt Vectors Vector No.
ATmega169P Table 11-2 on page 57 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2.
ATmega169P 0x0031 0x0032 out sei 0x0033 ... ... ... SPL,r16 ; Enable interrupts xxx ...
ATmega169P ; 11.2 0x1C2E RESET: ldi r16,high(RAMEND); Main program start 0x1C2F out SPH,r16 0x1C30 ldi r16,low(RAMEND) 0x1C31 0x1C32 out sei SPL,r16 0x1C33 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table, see ”MCUCR – MCU Control Register” on page 60.
ATmega169P Assembly Code Example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<
ATmega169P 12. External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT15..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles.
ATmega169P 12.2 12.2.1 Register Description EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control.
ATmega169P interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. 12.2.3 EIFR – External Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 PCIF1 PCIF0 – – – – – INTF0 Read/Write R/W R/W R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 0x1C (0x3C) EIFR • Bit 7 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15..
ATmega169P 12.2.5 PCMSK0 – Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 (0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK0 • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
ATmega169P 13. I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega169P 13.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 13-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET SLEEP WPx RRx SYNCHRONIZER D Q L Q D WRx RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 13.2.
ATmega169P 13.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 13.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
ATmega169P Figure 13-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega169P values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
ATmega169P 13.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega169P 13.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5 shows how the port pin control signals from the simplified Figure 13-2 on page 66 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 13-5.
ATmega169P Table 13-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
ATmega169P 13.3.1 Alternate Functions of Port A The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller. Table 13-3.
ATmega169P Table 13-5. 13.3.2 Overriding Signals for Alternate Functions in PA3..
ATmega169P • OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external interrupt source.
ATmega169P low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit. PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source. Table 13-7 and Table 13-8 on page 77 relate the alternate functions of Port B to the overriding signals shown in Figure 13-5 on page 71.
ATmega169P Table 13-8. 13.3.3 Overriding Signals for Alternate Functions in PB3..
ATmega169P Table 13-10 and Table 13-11 relate the alternate functions of Port C to the overriding signals shown in Figure 13-5 on page 71. Table 13-10. Overriding Signals for Alternate Functions in PC7..
ATmega169P 13.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-12. Table 13-12.
ATmega169P Table 13-13 and Table 13-14 relates the alternate functions of Port D to the overriding signals shown in Figure 13-5 on page 71. Table 13-13. Overriding Signals for Alternate Functions PD7..
ATmega169P 13.3.5 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-15. Table 13-15.
ATmega169P • XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART operates in synchronous mode. AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.
ATmega169P Table 13-17.
ATmega169P • TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In other states the pin is pulled high. • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5.
ATmega169P Table 13-20. Overriding Signals for Alternate Functions in PF3:PF0 13.3.7 Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT Alternate Functions of Port G The alternate pin configuration is as follows: Table 13-21.
ATmega169P • SEG4 – Port G, Bit 2 SEG4, LCD front plane 4 • SEG13 – Port G, Bit 1 SEG13, Segment driver 13 • SEG14 – Port G, Bit 0 SEG14, LCD front plane 14 Table 13-21 on page 85 and Table 13-22 relates the alternate functions of Port G to the overriding signals shown in Figure 13-5 on page 71. Table 13-22.
ATmega169P Table 13-23.
ATmega169P 13.4 13.4.1 Register Description for I/O-Ports MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD - - PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
ATmega169P 13.4.8 PORTC – Port C Data Register Bit 13.4.9 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC – Port C Data Direction Register Bit 13.4.
ATmega169P 13.4.16 PINE – Port E Input Pins Address Bit 7 6 5 4 3 2 1 0 PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 0x0C (0x2C) 13.4.17 PORTF – Port F Data Register Bit 13.4.
ATmega169P 14. 8-bit Timer/Counter0 with PWM 14.1 Features • • • • • • • 14.2 Single Compare Unit Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator External Event Counter 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) Overview Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block diagram is shown in Figure 14-1.
ATmega169P The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0A). See ”Output Compare Unit” on page 93. for details. The compare match event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. 14.2.
ATmega169P Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
ATmega169P Figure 14-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnx1:0 The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence.
ATmega169P 14.5.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform generation.
ATmega169P The design of the Output Compare pin logic allows initialization of the OC0A state before the output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of operation. See ”8-bit Timer/Counter Register Description” on page 102. 14.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM modes.
ATmega169P The timing diagram for the CTC mode is shown in Figure 14-5. The counter value (TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 14-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag.
ATmega169P In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0.
ATmega169P feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 14.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM.
ATmega169P set as output. The PWM waveform is generated by clearing (or setting) the OC0A Register at the compare match between OCR0A and TCNT0 when the counter increments, and setting (or clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter decrements.
ATmega169P Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 14-10 shows the setting of OCF0A in all modes except CTC mode. Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 14-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 14-11.
ATmega169P 14.9 8-bit Timer/Counter Register Description 14.9.1 TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode.
ATmega169P When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. Table 14-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 14-3. Compare Output Mode, non-PWM Mode COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected.
ATmega169P Table 14-6. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
ATmega169P • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, that is, when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
ATmega169P 15. 16-bit Timer/Counter1 15.1 Features • • • • • • • • • • • 15.
ATmega169P Figure 15-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 15.2.1 TCCRnB 1.
ATmega169P put Compare Units” on page 115. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See ”AC - Analog Comparator” on page 212.
ATmega169P 15.3 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
ATmega169P the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega169P The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega169P 15.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surroundings. Figure 15-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega169P The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit.
ATmega169P tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers” on page 109. 15.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
ATmega169P cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 15.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle.
ATmega169P prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
ATmega169P 15.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 15-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega169P 15.8.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 15-1 on page 128.
ATmega169P The timing diagram for the CTC mode is shown in Figure 15-6. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 15-6.
ATmega169P 15.9.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x, and set at BOTTOM.
ATmega169P or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
ATmega169P 15.9.4 Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.
ATmega169P The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
ATmega169P 15.9.5 Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.
ATmega169P Figure 15-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM).
ATmega169P The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase and frequency correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 15.
ATmega169P BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 15-12. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 15-13 shows the same timing data, but with the prescaler enabled. Figure 15-13.
ATmega169P 15.11 16-bit Timer/Counter Register Description 15.11.1 TCCR1A – Timer/Counter1 Control Register A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x80) TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A • Bit 5:4 – COM1B1:0: Compare Output Mode for Unit B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior.
ATmega169P Table 15-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 15-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 9 or 11: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
ATmega169P Waveform Generation Mode Bit Description(1) Table 15-4.
ATmega169P When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
ATmega169P FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 15.11.
ATmega169P 15.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 (0x87) ICR1[15:8] (0x86) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
ATmega169P 15.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
ATmega169P 16. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.1 Prescaler Reset The prescaler is free running, that is, operates independently of the Clock Select logic of the Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0.
ATmega169P Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle.
ATmega169P 16.4 16.4.1 Register Description GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSR2 PSR10 Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode.
ATmega169P 17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • • • • • • • 17.
ATmega169P (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value.
ATmega169P Figure 17-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 Timer/Counter clock. top Signalizes that TCNT2 has reached maximum value.
ATmega169P Figure 17-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnx1:0 The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare Register to either top or bottom of the counting sequence.
ATmega169P The setup of the OC2A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2A value is to use the Force Output Compare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2A1:0 bits are not double buffered together with the compare value. Changing the COM2A1:0 bits will take effect immediately. 17.
ATmega169P 17.5.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2A1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2A1:0 = 0 tells the Waveform Generator that no action on the OC2A Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 17-3 on page 154. For fast PWM mode, refer to Table 17-4 on page 154, and for phase correct PWM refer to Table 17-5 on page 154.
ATmega169P Figure 17-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega169P PWM mode is shown in Figure 17-6. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 17-6.
ATmega169P 17.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match between TCNT2 and OCR2A while upcounting, and set on the compare match while downcounting.
ATmega169P clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ----------------N ⋅ 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega169P 17.7 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 17-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.
ATmega169P Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 17-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 17-11.
ATmega169P 17.8 17.8.1 Asynchronous operation of the Timer/Counter Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: a. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2. b.
ATmega169P from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value.
ATmega169P 17.9 Timer/Counter Prescaler Figure 17-12. Prescaler for Timer/Counter2 PSR2 clkT2S/1024 clkT2S/256 clkT2S/128 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
ATmega169P 17.10 8-bit Timer/Counter Register Description 17.10.1 TCCR2A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
ATmega169P Table 17-3. Compare Output Mode, non-PWM Mode COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Toggle OC2A on compare match. 1 0 Clear OC2A on compare match. 1 1 Set OC2A on compare match. Table 17-4 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 17-4. Compare Output Mode, Fast PWM Mode(1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected.
ATmega169P • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 17-6. Table 17-6. 17.10.2 Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped).
ATmega169P 17.10.4 TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x70) – – – – – – OCIE2A TOIE2 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK2 • Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled.
ATmega169P 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin.
ATmega169P 18. SPI – Serial Peripheral Interface 18.1 Features • • • • • • • • 18.
ATmega169P The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
ATmega169P When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 18-1. For more details on automatic port overrides, refer to ”Alternate Port Functions” on page 71. Table 18-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
ATmega169P Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
ATmega169P The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega169P 18.3 18.3.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega169P 18.4 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 18-3 and Figure 18-4. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 18-3 on page 165 and Table 18-4 on page 165, as done below: Table 18-2.
ATmega169P 18.5 18.5.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
ATmega169P • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 18-5. 18.5.
ATmega169P 18.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
ATmega169P 19. USART 19.1 Features • • • • • • • • • • • • 19.
ATmega169P Figure 19-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1. Refer to Figure 1-1 on page 2, Table 13-13 on page 80, and Table 13-7 on page 76 for USART pin placement.
ATmega169P 19.2.1 AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer.
ATmega169P Figure 19-2. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 UCPOL txclk UMSEL 1 xcko DDR_XCK 1 1 0 rxclk Signal description: 19.3.1 txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal).
ATmega169P Table 19-1.
ATmega169P 19.3.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 19-3. Synchronous Mode XCK Timing.
ATmega169P Figure 19-4. Frame Formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPM1n:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting.
ATmega169P 19.5 USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization.
ATmega169P For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example(1) USART_Init: ; Set baud rate sts UBRRH0, r17 sts UBRRL0, r16 ; Enable receiver and transmitter ldi r16, (1<
ATmega169P 19.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
ATmega169P 19.6.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
ATmega169P 19.6.3 Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register.
ATmega169P 19.7 Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock.
ATmega169P 19.7.2 Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8n bit in UCSRnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn Status Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change.
ATmega169P Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSR0A, RXC0 rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSR0A in r17, UCSR0B in r16, UDR0 ; If error, return -1 andi r18,(1<
ATmega169P 19.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
ATmega169P 19.7.5 Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1n) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPM0n bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits.
ATmega169P 19.8 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver.
ATmega169P Figure 19-6. Sampling of Data and Parity Bit RxD BIT n Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Sample (U2X = 1) 1 2 3 4 5 6 7 8 1 The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. The center samples are emphasized on the figure by having the sample number inside boxes.
ATmega169P The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. ( D + 1 )S R slow = ------------------------------------------S – 1 + D ⋅ S + SF ( D + 2 )S R fast = ----------------------------------( D + 1 )S + S M D Sum of character size and parity size (D = 5 to 10 bit). S Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode. SF First sample number used for majority voting.
ATmega169P The recommendations of the maximum receiver baud rate error was made under the assumption that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the receivers baud rate error. The Receiver’s system clock (XTAL) will always have some minor instability over the supply voltage range and the temperature range.
ATmega169P 5. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and waits for a new address frame from master. The process then repeats from 2. Using any of the 5-bit to 8-bit character frame formats is possible, but impractical since the Receiver must change between using n and n+1 character frame formats. This makes fullduplex operation difficult since the Transmitter and Receiver uses the same character size setting.
ATmega169P 19.10 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRRn settings in Table 19-4. UBRRn values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
ATmega169P Table 19-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz Baud Rate (bps) U2Xn = 0 fosc = 4.0000 MHz U2Xn = 1 U2Xn = 0 fosc = 7.3728 MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.
ATmega169P Table 19-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.
ATmega169P Table 19-7. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.
ATmega169P 19.11 USART Register Description 19.11.1 UDRn – USART I/O Data Register Bit 7 6 5 4 (0xC6) 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
ATmega169P UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error n This bit is set if the next character in the receive buffer had a Frame Error when received, that is, when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA.
ATmega169P • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxD pin when enabled.
ATmega169P Receiver will generate a parity value for the incoming data and compare it to the UPM0n setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 19-9. UPM Bits Settings UPMn1 UPMn0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 19-10.
ATmega169P 19.11.5 UBRRLn and UBRRHn – USART Baud Rate Registers Bit 15 14 13 12 (0xC5) – – – – (0xC4) Initial Value 10 9 8 UBRRn[11:8] UBRRHn UBRRn[7:0] 7 Read/Write 11 6 5 4 3 UBRRLn 2 1 0 R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRHn is written.
ATmega169P 20. USI – Universal Serial Interface The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. The main features of the USI are: • • • • • • 20.
ATmega169P an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus.
ATmega169P Figure 20-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 20-3 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
ATmega169P rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register.
ATmega169P 20.2.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
ATmega169P 20.2.4 Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 20-4.
ATmega169P Figure 20-5. Two-wire Mode, Typical Timing Diagram SDA SCL S A B 1-7 8 9 1-8 9 1-8 9 ADDRESS R/W ACK DATA ACK DATA ACK C D E P F Referring to the timing diagram (Figure 20-5), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero.
ATmega169P 20.2.5 Start Condition Detector The start condition detector is shown in Figure 20-6 on page 205 The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time.
ATmega169P 20.4 USI Register Descriptions 20.4.1 USIDR – USI Data Register Bit 7 6 5 4 3 2 1 0 (0xBA) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USIDR The USI uses no buffering of the Serial Register, that is, when accessing the Data Register (USIDR) the Serial Register is accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed.
ATmega169P A counter overflow interrupt will wakeup the processor from Idle sleep mode. • Bit 5 – USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is useful when implementing Two-wire bus master arbitration.
ATmega169P nally, and data input sampled, even when outputs are disabled. The relations between USIWM1:0 and the USI operation is summarized in Table 20-1 on page 210.
ATmega169P Table 20-1. Relations between USIWM1:0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
ATmega169P Table 20-2 shows the relationship between the USICS1:0 and USICLK setting and clock source used for the Shift Register and the 4-bit counter. Table 20-2.
ATmega169P 21. AC - Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega169P 21.1 Analog Comparator Multiplexed Input It is possible to select any of the ADC7:0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature.
ATmega169P 21.2 21.2.1 Analog Comparator Register Description ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – ACME – – – ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator.
ATmega169P Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set.
ATmega169P 22. ADC - Analog to Digital Converter 22.1 Features • • • • • • • • • • • • • 22.2 10-bit Resolution 0.5 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 13 µs - 260 µs Conversion Time (50 kHz to 1 MHz ADC clock) Up to 15 ksps at Maximum Resolution (200 kHz ADC clock) Eight Multiplexed Single Ended Input Channels Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.
ATmega169P Figure 22-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS0 ADPS1 ADIF ADPS2 ADATE ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL.
ATmega169P If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
ATmega169P If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 22.5 Prescaling and Conversion Timing Figure 22-3.
ATmega169P In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 22-1 on page 221. Figure 22-4.
ATmega169P Figure 22-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete Table 22-1. MUX and REFS Update ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 Condition Auto Triggered conversions 22.
ATmega169P 22.6.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
ATmega169P 22.7.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 22-8 An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
ATmega169P 22.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b.
ATmega169P 22.7.3 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 22-10.
ATmega169P Figure 22-12. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 22-13.
ATmega169P 22.8 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN ⋅ 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 22-3 on page 229 and Table 22-4 on page 230). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
ATmega169P Table 22-2. Correlation Between Input Voltage and Output Codes VADCn Read Code VADCm + VREF 0x1FF 511 VADCm + 511/512 VREF 0x1FF 511 VADCm + 510/512 VREF 0x1FE 510 ... ... ... VADCm + /512 VREF 0x001 1 VADCm 0x000 0 VADCm - 1/512 VREF 0x3FF -1 ... ... ... 1 VADCm - 511 /512 VREF VADCm - VREF Corresponding Decimal Value 0x201 -511 0x200 -512 ADMUX = 0xFB (ADC3 - ADC2, 1.1V reference, left adjusted result). Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
ATmega169P 22.9 22.9.1 ADC Register Description ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 22-3.
ATmega169P Table 22-4. Input Channel Selections MUX4..
ATmega169P 22.9.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega169P Table 22-5. 22.9.3 22.9.3.
ATmega169P 22.9.4 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – ACME – – – ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 7 – Res: Reserved Bit This bit is reserved for future use. To ensure compatibility with future devices, this bit must be written to zero when ADCSRB is written.
ATmega169P 23. LCD Controller 23.1 Features • • • • • • • • • • • • 23.
ATmega169P Figure 23-1.
ATmega169P To energize a segment, an absolute voltage above a certain threshold must be applied. This is done by letting the output voltage on corresponding COM pin and SEG pin have opposite phase. For display with more than one common, one (1/2 bias) or two (1/3 bias) additional voltage levels must be applied. Otherwise, non-energized segments on COM0 would be energized for all non-selected common.
ATmega169P 23.2.8 Minimizing Power Consumption By keeping the percentage of the time the LCD drivers are turned on at a minimum, the power consumption of the LCD driver can be minimized. This can be achieved by using the lowest acceptable frame rate, and using low power waveform if possible. The drive time should be kept at the lowest setting that achieves satisfactory contrast for a particular display, while allowing some headroom for production variations between individual LCD drivers and displays.
ATmega169P Figure 23-4.
ATmega169P 23.3.3 1/3 Duty and 1/3 Bias 1/3 bias is usually recommended for LCD with three common terminals (1/3 duty). Waveform is shown in Figure 23-5. SEG0 - COM0 is the voltage across a segment that is on and SEG0COM1 is the voltage across a segment that is off. Figure 23-5.
ATmega169P 23.3.5 Low Power Waveform To reduce toggle activity and hence power consumption a low power waveform can be selected by writing LCDAB to one. Low power waveform requires two subsequent frames with the same display data to obtain zero DC voltage. Consequently data latching and Interrupt Flag is only set every second frame. Default and low power waveform is shown in Figure 23-7 for 1/3 duty and 1/3 bias. For other selections of duty and bias, the effect is similar. Figure 23-7.
ATmega169P 23.3.8 Port Mask For LCD with less than 25 segment terminals, it is possible to mask some of the unused pins and use them as ordinary port pins instead. Refer to Table 23-3 on page 247 for details. Unused common pins are automatically configured as port pins.
ATmega169P 23.4 LCD Usage The following section describes how to use the LCD. 23.4.1 LCD Initialization Prior to enabling the LCD some initialization must be preformed. The initialization process normally consists of setting the frame rate, duty, bias and port mask. LCD contrast is set initially, but can also be adjusted during operation. Consider the following LCD as an example: Figure 23-8. LCD usage example.
ATmega169P Assembly Code Example(1) LCD_Init: ; Use 32 kHz crystal oscillator ; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins ldi r16, (1<
ATmega169P In the example below we assume SEG10 and COM1 and SEG4 in COM0 are the only segments changed from frame to frame. Data are stored in r20 and r21 for simplicity Assembly Code Example(1) LCD_update: ; LCD Blanking and Low power waveform are unchanged. ; Update Display memory. sts LCDDR0, r20 sts LCDDR6, r21 ret C Code Example(1) Void LCD_update(unsigned char data1, data2); { /* LCD Blanking and Low power waveform are unchanged. */ /* Update Display memory.
ATmega169P Assembly Code Example(1) LCD_disable: ; Wait until a new frame is started. Wait_1: lds r16, LCDCRA sbrs r16, LCDIF rjmp Wait_1 ; Set LCD Blanking and clear interrupt flag ; by writing a logical one to the flag. ldi r16, (1<
ATmega169P 23.5 23.5.1 LCD Register Description LCDCRA – LCD Control and Status Register A Bit 7 6 5 4 3 2 1 0 LCDEN LCDAB – LCDIF LCDIE LCDBD LCDCCD LCDBL Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xE4) LCDCRA • Bit 7 – LCDEN: LCD Enable Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is turned off immediately.
ATmega169P • Bit 0 – LCDBL: LCD Blanking When this bit is written to one, the display will be blanked after completion of a frame. All segment and common pins will be driven to ground. 23.5.
ATmega169P Table 23-3. 23.5.
ATmega169P • Bit 3 – Res: Reserved Bit This bit is reserved and will always read as zero. • Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0 The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are shown in Table 23-5. This Clock Divider gives extra flexibility in frame rate selection. Table 23-5. LCD Clock Divide LCDCD2 LCDCD1 LCDCD0 Output from Prescaler divided by (D): clkLCD = 32.
ATmega169P 23.5.4 LCDCCR – LCD Contrast Control Register Bit 7 6 5 4 3 2 1 0 LCDDC2 LCDDC1 LCDDC0 LCDMDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xE7) LCDCCR • Bits 7:5 – LCDDC2:0: LDC Display Configuration The LCDDC2:0 bits determine the amount of time the LCD drivers are turned on for each voltage transition on segment and common pins.
ATmega169P Table 23-8. 23.5.5 LCD Contrast Control LCDCC3 LCDCC2 LCDCC1 LCDCC0 Maximum Voltage VLCD 0 0 0 0 2.60V 0 0 0 1 2.65V 0 0 1 0 2.70V 0 0 1 1 2.75V 0 1 0 0 2.80V 0 1 0 1 2.85V 0 1 1 0 2.90V 0 1 1 1 2.95V 1 0 0 0 3.00V 1 0 0 1 3.05V 1 0 1 0 3.10V 1 0 1 1 3.15V 1 1 0 0 3.20V 1 1 0 1 3.25V 1 1 1 0 3.30V 1 1 1 1 3.
ATmega169P 24. JTAG Interface and On-chip Debug System 24.0.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega169P 24.2 TAP – Test Access Port The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are: • TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine. • TCK: Test Clock. JTAG operation is synchronous to TCK. • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out.
ATmega169P Figure 24-1.
ATmega169P Figure 24-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 24.
ATmega169P • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, PauseIR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
ATmega169P A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in ”On-chip Debug Specific JTAG Instructions” on page 257. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system to work.
ATmega169P 24.7 24.7.1 On-chip Debug Related Register in I/O Memory OCDR – On-chip Debug Register Bit 7 6 5 4 3 2 1 0 0x31 (0x51) MSB/IDRD LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
ATmega169P 25. IEEE 1149.1 (JTAG) Boundary-scan 25.1 Features • • • • • 25.2 JTAG (IEEE std. 1149.
ATmega169P 25.3 Data Registers The Data Registers relevant for Boundary-scan operations are: • Bypass Register • Device Identification Register • Reset Register • Boundary-scan Chain 25.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state.
ATmega169P Figure 25-2. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 25.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See ”Boundary-scan Chain” on page 262 for a complete description. 25.
ATmega169P The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input. 25.4.3 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
ATmega169P Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn. Digital alternate port functions are connected outside the dotted box in Figure 25-4 on page 264 to make the scan chain read the actual pin value. For Analog function, there is a direct connection from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog circuitry. Figure 25-3.
ATmega169P Figure 25-4.
ATmega169P 25.5.2 Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 25-5 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV. Figure 25-5. Observe-only Cell To Next Cell ShiftDR From System Pin To System Logic FF1 0 D Q 1 From Previous Cell 25.5.
ATmega169P Table 25-1 summaries the scan registers for the external clock pin XTAL1, oscillators with XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator. Table 25-1. Enable Signal Scanned Clock Line Clock Option Scanned Clock Line when not Used EXTCLKEN EXTCLK (XTAL1) External Clock 0 OSCON OSCCK External Crystal External Ceramic Resonator 1 OSC32EN OSC32CK Low Freq. External Crystal 1 Notes: 25.5.4 Scan Signals for the Oscillator(1)(2)(3) 1.
ATmega169P Figure 25-8. General Boundary-scan cell Used for Signals for Comparator and ADC To Next Cell ShiftDR EXTEST From Digital Logic/ From Analog Ciruitry 0 1 To Analog Circuitry/ To Digital Logic 0 D Q D Q 1 G From Previous Cell Table 25-2.
ATmega169P 25.5.5 Scanning the ADC Figure 25-9 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 25-5 on page 265 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 25-9. Analog to Digital Converter. VCCREN AREF IREFEN 1.
ATmega169P Table 25-3.
ATmega169P Table 25-3. Signal Name Boundary-scan Signals for the ADC(1) Direction as Seen from the ADC Description Recommended Input when not in use Output Values when Recommended Inputs are Used, and CPU is not Using the ADC HOLD Input Sample & Hold signal. Sample analog signal when low. Hold signal when high. If differential amplifier is used, this signal must go active when ACLK is high.
ATmega169P Note: 1. Incorrect setting of the switches in Figure 25-9 on page 268 will make signal contention and may damage the part. There are several input choices to the S&H circuitry on the negative input of the output comparator in Figure 25-9 on page 268. Make sure only one path is selected from either one ADC pin, Bandgap reference source, or Ground. If the ADC is not to be used during scan, the recommended input values from Table 25-3 on page 269 should be used.
ATmega169P Table 25-4. Algorithm for Using the ADC PA3. Control PA3. Pull-up_ Enable MUXEN HOLD PRECH PA3.
ATmega169P Table 25-5.
ATmega169P Table 25-5. ATmega169P Boundary-scan Order Bit Number Signal Name 157 PE0.Data 156 PE0.Control 155 PE0.Pull-up_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pull-up_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pull-up_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pull-up_Enable 145 PE4.Data 144 PE4.Control 143 PE4.Pull-up_Enable 142 PE5.Data 141 PE5.Control 140 PE5.Pull-up_Enable 139 PE6.Data 138 PE6.Control 137 PE6.Pull-up_Enable 136 PE7.Data 135 PE7.
ATmega169P Table 25-5. ATmega169P Boundary-scan Order Bit Number Signal Name Module 132 PB0.Control 131 PB0.Pull-up_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pull-up_Enable 127 PB2.Data 126 PB2.Control 125 PB2.Pull-up_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pull-up_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pull-up_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pull-up_Enable 115 PB6.Data 114 PB6.Control 113 PB6.Pull-up_Enable 112 PB7.Data 111 PB7.
ATmega169P Table 25-5. ATmega169P Boundary-scan Order Bit Number Signal Name 96 EXTCLK (XTAL1) 95 OSCCK 94 RCCK 93 OSC32CK 92 PD0.Data 91 PD0.Control 90 PD0.Pull-up_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pull-up_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pull-up_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pull-up_Enable 80 PD4.Data 79 PD4.Control 78 PD4.Pull-up_Enable 77 PD5.Data 76 PD5.Control 75 PD5.Pull-up_Enable 74 PD6.Data 73 PD6.Control 72 PD6.
ATmega169P Table 25-5. ATmega169P Boundary-scan Order Bit Number Signal Name 60 PC0.Pull-up_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pull-up_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pull-up_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pull-up_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pull-up_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pull-up_Enable 44 PC6.Data 43 PC6.Control 42 PC6.Pull-up_Enable 41 PC7.Data 40 PC7.Control 39 PC7.Pull-up_Enable 38 PG2.Data 37 PG2.
ATmega169P Table 25-5. ATmega169P Boundary-scan Order Bit Number Signal Name 24 PA4.Pull-up_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pull-up_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pull-up_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pull-up_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.Control 6 PF2.Pull-up_Enable 5 PF1.Data 4 PF1.Control 3 PF1.Pull-up_Enable 2 PF0.Data 1 PF0.
ATmega169P 25.8 25.8.1 Boundary-scan Related Register in I/O Memory MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD - - PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.
ATmega169P 26. Boot Loader Support – Read-While-Write Self-Programming 26.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 26.2 1. A page is a section in the Flash consisting of several bytes (see Table 27-7 on page 299) used during programming.
ATmega169P 26.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section.
ATmega169P Figure 26-1. Read-While-Write vs.
ATmega169P Figure 26-2.
ATmega169P 26.5 Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: • To protect the entire Flash from a software update by the MCU. • To protect only the Boot Loader Flash section from a software update by the MCU.
ATmega169P 26.6 Entering the Boot Loader Program Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code.
ATmega169P 26.7 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 27-7 on page 299), the Program Counter can be treated as having two different sections.
ATmega169P 26.8 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
ATmega169P 26.8.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • Page Write to the RWW section: The NRWW section can be read during the Page Write. • Page Write to the NRWW section: The CPU is halted during the operation. 26.8.
ATmega169P 26.8.8 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 26.8.
ATmega169P 26.8.10 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
ATmega169P 26.8.12 Boot Loader: Simple Assembly Code Example ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
ATmega169P sbiw loophi:looplo, 1 brne Rdloop ;use subi for PAGESIZEB<=256 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega169P Table 26-7. Read-While-Write Limit(1) Section Pages Address Read-While-Write section (RWW) 112 0x0000 - 0x1BFF No Read-While-Write section (NRWW) 16 0x1C00 - 0x1FFF Note: 1. For details about these two section, see ”NRWW – No Read-While-Write Section” on page 281 and ”RWW – Read-While-Write Section” on page 281. Table 26-8.
ATmega169P 26.9 26.9.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega169P • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
ATmega169P 27. Memory Programming 27.1 Program And Data Memory Lock Bits The ATmega169P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 27-1.
ATmega169P Lock Bit Protection Modes(1)(2) (Continued) Table 27-2. Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega169P Table 27-4. Fuse High Byte Fuse High Byte Bit No Description Default Value (4) OCDEN 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega169P 27.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 27.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
ATmega169P When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 27-12 on page 301. Figure 27-1. Parallel Programming +5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12V BS2 VCC +5V AVCC PB7 - PB0 DATA RESET PA0 XTAL1 GND Table 27-9. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command.
ATmega169P Table 27-11. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 27-12.
ATmega169P 27.7 27.7.1 Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5V - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 27-10 on page 300 to “0000” and wait at least 100 ns. 4. Apply 11.5V - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5.
ATmega169P A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B. Load Address Low byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “0”. This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1.
ATmega169P J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 27-2.
ATmega169P 27.7.5 Programming the EEPROM The EEPROM is organized in pages, see Table 27-8 on page 299. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to ”Programming the Flash” on page 302 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
ATmega169P 27.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash” on page 302 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 27.7.
ATmega169P Figure 27-5. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 27.7.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on page 302 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte.
ATmega169P Figure 27-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte BS1 1 BS2 27.7.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to ”Programming the Flash” on page 302 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS to “0”.
ATmega169P Figure 27-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 27-7 on page 308 (that is, tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 27-9.
ATmega169P Table 27-13.
ATmega169P 27.8.1 Serial Programming Pin Mapping Table 27-14. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB2 I Serial Data in MISO PB3 O Serial Data out SCK PB1 I Serial Clock Figure 27-10. Serial Programming and Verify(1) +1.8V - 5.5V VCC +1.8V - 5.5V(2) MOSI AVCC MISO SCK XTAL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.
ATmega169P case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction.
ATmega169P Figure 27-11.
ATmega169P 27.8.3 Serial Programming Instruction set Table 27-16 and Figure 27-12 on page 315 describes the Instruction set. Table 27-16.
ATmega169P Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 27-12. Figure 27-12.
ATmega169P 27.9 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
ATmega169P Figure 27-13. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 27.9.2 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
ATmega169P 27.9.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register. • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.
ATmega169P 27.9.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section ”Programming Specific JTAG Instructions” on page 316. The Data Registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register 27.9.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming.
ATmega169P Figure 27-15.
ATmega169P Table 27-17. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b.
ATmega169P Table 27-17. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 6b. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c.
ATmega169P Table 27-17. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext. byte Fuse High byte Fuse Low byte Lock bits 9a.
ATmega169P Figure 27-16. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 27.9.
ATmega169P ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 27-17.
ATmega169P 27.9.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 27-13 on page 309). 27.9.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 326. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3.
ATmega169P 27.9.17 Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b and 3c. 4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3.
ATmega169P 27.9.20 Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data high byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. 4. Write Fuse High byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 27-13 on page 309). 6.
ATmega169P 28. Electrical Characteristics 28.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATmega169P TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Power Supply Current(5) ICC (6) Power-save mode Power-down mode(6) Typ. Max. Active 1 MHz, VCC = 2V 0.35 0.44 Active 4 MHz, VCC = 3V 2.3 2.5 Active 8 MHz, VCC = 5V 8.4 9.5 Idle 1 MHz, VCC = 2V 0.1 0.2 Idle 4 MHz, VCC = 3V 0,7 0.8 Idle 8 MHz, VCC = 5V 3.0 3.3 32 kHz TOSC enabled, VCC = 1.8V 0.55 1.6 32 kHz TOSC enabled, VCC = 3V 0.8 2.
ATmega169P 28.3 Speed Grades Maximum frequency is depending on VCC. As shown in Figure 28-1 and Figure 28-2 on page 332, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 4.5V. To calculate the maximum frequency at a given voltage in this interval, use this equation: Frequency = a • ( V – Vx ) + Fy To calculate required voltage for a given frequency, use this equation:: Voltage = b • ( F – Fy ) + Vx Table 28-1. Constants used to calculate maximum speed vs.
ATmega169P Figure 28-2. Maximum Frequency vs. VCC, ATmega169P 16 MHz 8 MHz Safe Operating Area 2.7V 28.4 28.4.1 4.5V 5.5V Clock Characteristics Calibrated Internal RC Oscillator Accuracy Table 28-2. Calibration Accuracy of Internal RC Oscillator Factory Calibration Frequency VCC 8.0 MHz 3V Temperature Calibration Accuracy 25°C ±10% -40°C - 85°C ±1% (1) User Calibration Notes: 28.4.2 1.8V - 5.5V 2.7V - 5.5V(2) 7.3 MHz - 8.1 MHz 1. Voltage range for ATmega169PV. 2.
ATmega169P 28.4.3 External Clock Drive Table 28-3. External Clock Drive VCC = 1.8V - 5.5V 28.5 VCC = 2.7V - 5.5V VCC = 4.5V - 5.5V Symbol Parameter Min. Max. Min. Max. Min. Max. Units 1/tCLCL Oscillator Frequency 0 1 0 8 0 16 MHz tCLCL Clock Period 1000 125 62.5 tCHCX High Time 400 50 25 tCLCX Low Time 400 50 25 tCLCH Rise Time 2.0 1.6 0.5 tCHCL Fall Time 2.0 1.6 0.
ATmega169P Table 28-5. BODLEVEL Fuse Coding(1) BODLEVEL 2..0 Fuses Min VBOT Typ VBOT 111 Max VBOT Units BOD Disabled 110 1.7 1.8 2.0 101 2.5 2.7 2.9 100 4.1 4.3 4.5 V 011 010 Reserved 001 000 Note: 28.6 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test.
ATmega169P Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12 MHz - 3 tCLCL for fCK > 12 MHz Figure 28-4. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 8 7 MOSI (Data Output) MSB ... LSB Figure 28-5. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ...
ATmega169P 28.7 ADC Characteristics – Preliminary Data Table 28-7. Symbol ADC Characteristics Parameter Condition Min Typ Max Units Single Ended Conversion 10 Differential Conversion 8 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz 4.
ATmega169P Table 28-7. Symbol ADC Characteristics Parameter Condition Min Typ Max Units 1.0 1.1 1.2 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Note: 1. Voltage difference between channels. 28.8 LCD Controller Characteristics Table 28-8.
ATmega169P 29. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
ATmega169P Figure 29-2. Active Supply Current vs. Frequency (1 MHz MHz - 20 MHz) 1 MHz - 20 25 5.5V 20 5.0V ICC (mA) 4.5V 15 4.0V 10 3.3V 5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 29-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz 10 85°C 25°C -40°C 9 8 ICC (mA) 7 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P Figure 29-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 2 85°C 25°C -40°C 1.8 1.6 ICC (mA) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-5. Active Supply Current vs. VCC (32 kHz Watch Crystal) 50.0 25°C 45.0 40.0 ICC (µ A) 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P 29.2 Idle Supply Current Figure 29-6. Idle Supply Current vs. Frequency 0.1 MHz(0.1 - 1.0 MHz MHz - 1.0 MHz) 0.5 0.45 5.5V 0.4 5.0V ICC (mA) 0.35 4.5V 0.3 4.0V 0.25 0.2 3.3V 0.15 2.7V 0.1 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 29-7. Idle Supply Current vs. Frequency (1- MHz 1 MHz 20 MHz- 20 MHz) 10 9 5.5V ICC (mA) 8 7 5.0V 6 4.5V 5 4.0V 4 3 3.3V 2 2.7V 1 1.
ATmega169P Figure 29-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 4 85°C 25°C -40°C 3.5 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 0.7 85°C 25°C -40°C 0.6 ICC (mA) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P Figure 29-10. Idle Supply Current vs. VCC (32 kHz Watch Crystal) 14 25°C 12 I CC (µ A) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 42 for details. Table 29-1.
ATmega169P Table 29-2. Additional Current Consumption (percentage) in Active and Idle mode Additional Current consumption compared to Active with external clock (see Figure 29-1 on page 338 and Figure 29-2 on page 339) PRR bit Additional Current consumption compared to Idle with external clock (see Figure 29-6 on page 341 and Figure 29-7 on page 341) PRSPI 3.2% 10.8% PRTIM1 5.6% 18.6% PRLCD 12.5% 41.
ATmega169P Figure 29-12. Power-down Supply Current vs. TIMER VCC (Watchdog Timer Enabled) WATCHDOG ENABLED 20 85°C -40°C 25°C 18 16 14 ICC (µA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.5 Power-save Supply Current Figure 29-13. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 3.50 3.00 85°C ICC (µA) 2.50 -40°C 25°C 2.00 1.50 1.00 0.50 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
ATmega169P 29.6 Standby Supply Current Figure 29-14. Standby Supply Current vs. VCC (32 kHz Watch Crystal, Watchdog Timer Disabled) 2.50 85°C 2.00 25°C I CC (µ A) -40°C 1.50 1.00 0.50 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) Figure 29-15. Standby Supply Current vs. VCC (455 kHz Resonator, Watchdog Timer Disabled) 70 60 ICC (µA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P Figure 29-16. Standby Supply Current vs. VCC (1 MHz Resonator, Watchdog Timer Disabled) 60 50 ICC (µA) 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-17. Standby Supply Current vs. VCC (2 MHz Resonator, Watchdog Timer Disabled) 90 80 70 I CC (µ A) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P Figure 29-18. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled) 80 70 60 I CC (µ A ) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-19. Standby Supply Current vs. VCC (4 MHz Resonator, Watchdog Timer Disabled) 140 120 I CC (µ A ) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P Figure 29-20. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled) 140 120 ICC (µA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-21. Standby Supply Current vs. VCC (6 MHz Resonator, Watchdog Timer Disabled) 160 140 120 ICC (µA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P Figure 29-22. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled) 180 160 140 ICC (µA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.7 Pin Pull-up Figure 29-23. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs.
ATmega169P Figure 29-24. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 90 80 25°C 85°C 70 -40°C IIO (µA) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VIO (V) Figure 29-25. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 85°C 25°C IOP (µA) 40 -40°C 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169P Figure 29-26. Reset Pull-up Resistor CurrentVcc vs. Reset Pin Voltage (VCC = 5V) = 5V 120 -40°C 25°C 100 85°C IRESET (µA) 80 60 40 20 0 0 1 2 3 4 5 VRESET (V) Figure 29-27. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 70 60 -40°C 25°C IRESET (µA) 50 85°C 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega169P Figure 29-28. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 -40°C 35 25°C 30 IRESET (µA) 85°C 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) 29.8 Pin Driver Strength Figure 29-29. I/O Pin Source Current vs.
ATmega169P Figure 29-30. I/O Pin Source Current vs. Output Ports A, C, D, E, F, G (VCC = 2.7V) Vcc = Voltage, 2.7V 25 -40°C 25°C 20 IOH (mA) 85°C 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 29-31. I/O Pin Source Current vs. Output Ports A, C, D, E, F, G (VCC = 1.8V) Vcc = Voltage, 1.8V 8 -40°C 7 25°C 6 85°C IOH (mA) 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169P Figure 29-32. I/O Pin Source Current vs. Output Voltage, Port B (VCC= 5V) 80 70 -40°C 60 25°C 85°C IOH (mA) 50 40 30 20 10 0 0 1 2 3 4 VOH (V) Figure 29-33. I/O Pin Source Current vs. Output Port B (VCC = 2.7V) Vcc = Voltage, 2.7V 35 30 -40°C 25°C 25 IOH (mA) 85°C 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega169P Figure 29-34. I/O Pin Source Current vs. Output Port B (VCC = 1.8V) Vcc = Voltage, 1.8V 10 -40°C 9 25°C 8 85°C IOH (mA) 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) Figure 29-35. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G (VCC = 5V) 50 -40°C IOL (mA) 45 40 25°C 35 85°C 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169P Figure 29-36. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G (VCC = 2.7V) 20 -40°C 18 16 25°C IOL (mA) 14 85°C 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 29-37. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G (VCC = 1.8V) 7 -40°C 6 25°C IOL (mA) 5 85°C 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169P Figure 29-38. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 5V) 90 80 -40°C 70 25°C IOL (mA) 60 85°C 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 29-39. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 2.7V) 35 -40°C 30 25°C 25 IOL (mA) 85°C 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169P Figure 29-40. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 1.8V) 12 -40°C 10 25°C 8 I OL (m A ) 85°C 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) 29.9 Pin Thresholds and Hysteresis Figure 29-41. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 85°C 25°C -40°C 3 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P Figure 29-42. I/O Pin Input Threshold Voltage VCC VIL, I/O PINvs. READ AS (V '0' IL, I/O Pin Read as “0”) 3 85°C 25°C -40°C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-43. I/O Pin Input Hysteresis vs. VCC 0.6 -40°C 0.5 25°C Input hysteresis ( V) 0.4 85°C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P Figure 29-44. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.5 Threshold (V) 2 1.5 -40°C 25°C 85°C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-45. Reset Input Threshold Voltage vs.VOLTAGE VCC (VIL,Reset RESET INPUT THRESHOLD vs. VCC Pin Read as “0”) VIL, RESET PIN READ AS '0' 85°C 25°C -40°C 2.5 2.5 2 1.5 Threshold (V) Threshold (V) 2 1.5 -40°C 25°C 1 85°C 1 0.5 0.5 0 1.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2 2.5 3 3.
ATmega169P Figure 29-46. Reset Input Pin Hysteresis vs. VCC 0.7 -40°C 0.6 Input hysteresis ( V) 0.5 25°C 0.4 0.3 85°C 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.10 BOD Thresholds and Analog Comparator Offset Figure 29-47. BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.6 4.5 Rising VCC Threshol d ( V ) 4.4 Falling VCC 4.3 4.2 4.
ATmega169P Figure 29-48. BOD Thresholds vs. Temperature BODLEVEL(BOD IS 2.7VLevel is 2.7V) 3 2.9 Rising VCC Threshol d ( V ) 2.8 Falling VCC 2.7 2.6 2.5 2.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Figure 29-49. BOD Thresholds vs. Temperature (BOD Level is 1.8V) BODLEVEL IS 1.8V 2.1 2 Rising VCC Threshol d ( V ) 1.9 1.8 Falling VCC 1.7 1.6 1.
ATmega169P Figure 29-50. Bandgap Voltage vs. VCC CC 1.14 Bandgap Voltage ( V ) 1.13 1.12 85°C 25°C 1.11 -40°C 1.1 1.09 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 29-51. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) CC 0.008 85°C 25°C Comparator Offset Voltage ( V ) 0.006 -40°C 0.004 0.002 0 -0.002 -0.004 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169P Figure 29-52. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) CC 0.003 85°C Comparator Offset Voltage ( V ) 0.002 25°C 0.001 -40°C 0 -0.001 -0.002 -0.003 -0.004 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) 29.11 Internal Oscillator Speed Figure 29-53. Oscillator Current vs. VCC (32 kHz Watch Crystal) I CC (µ A) 1.00 0.90 85°C 0.80 25°C 0.70 -40°C 0.60 0.50 0.40 0.30 0.20 0.10 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
ATmega169P Figure 29-54. Watchdog Oscillator Frequency vs. VCC 1200 -40°C 25°C 85°C 1150 1100 FRC (kHz) 1050 1000 950 900 850 800 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-55. Calibrated8MHz 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.8 8.6 8.4 F RC (MHz) 8.2 8 7.8 7.6 7.4 1.8V 2.7V 4.0V 5.5V 7.
ATmega169P Figure 29-56. Calibrated 8 MHz RC Oscillator Frequency vs. VCC 10 9.5 FRC (MHz) 9 8.5 85°C 8 25°C 7.5 -40°C 7 6.5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure CALIBRATED 29-57. Calibrated 8 MHz Oscillator Frequency vs. Osccal Value 8 MHz RCRC OSCILLATOR FREQUENCY vs.
ATmega169P 29.12 Current Consumption of Peripheral Units Figure 29-58. Brownout Detector Current vs. VCC 30 -40°C 85°C 25°C 25 ICC (µA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-59. ADC Current vs. VCC (AREF = AVCC) CC 350 -40°C 25°C 85°C 300 ICC (µA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P Figure 29-60. AREF External Reference Current vs. VCC CC 85°C 25°C -40°C 160 140 120 IAREF (µA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) The differential current consumption between Power-save with WD disabled and 32 kHz TOSC represents the current drawn by Timer/Counter2. Figure 29-61. Watchdog Timer Current vs. VCC 16 85°C 25°C -40°C 14 12 ICC (µA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P Figure 29-62. Analog Comparator Current vs. VCC 120 100 -40°C 80 25°C I CC (µ A ) 85°C 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-63. Programming Current vs. VCC 25 -40°C 20 25°C ICC (mA) 15 85°C 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P 29.13 Current Consumption in Reset and Reset Pulsewidth Figure 29-64. Reset Supply Current vs. VCC (0.1 MHz - 1.0 MHz, Excluding Current Through The Reset Pull-up) 0.18 5.5V I CC (mA ) 0.16 0.14 5.0V 0.12 4.5V 0.1 4.0V 0.08 3.3V 0.06 2.7V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 29-65. Reset Supply Current vs. VCC (1 MHz - 20 MHz, Excluding Current Through The Reset Pull-up) I CC (mA ) 3.5 3 5.5V 2.5 5.0V 4.5V 2 4.0V 1.
ATmega169P Figure 29-66. Minimum Reset Pulse Width vs. VCC 2500 Pulsewidth (ns) 2000 1500 1000 500 85°C 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169P 30.
ATmega169P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBF) Reserved – – – – – – – – Page (0xBE) Reserved – – – – – – – – (0xBD) Reserved – – – – – – – – (0xBC) Reserved – – – – – – – – (0xBB) Reserved – – – – – – – – (0xBA) USIDR (0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 207 (0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 208 (0xB7) Reserved – – – –
ATmega169P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7D) Reserved – – – – – – – – (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 229 (0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 214, 233 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH ADC Data Register High byte Page 231 232 (0x78) ADCL (0x77) Reserved – – – ADC Data Register Low byte – – – – – 232 (0x76) Reserved – – – – – – –
ATmega169P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1B (0x3B) Reserved – – – – – – – – Page 0x1A (0x3A) Reserved – – – – – – – – 0x19 (0x39) Reserved – – – – – – – – 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) TIFR2 – – – – – – OCF2A TOV2 156 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 134 0x15 (0x35) TIFR0 – – – – – – OCF0A TOV0 105 0x14 (0x34) PORTG – – PORTG5 PORTG4 PORTG3 PORTG2 POR
ATmega169P 31.
ATmega169P Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1)
ATmega169P Mnemonics Operands Description Operation Flags #Clocks PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
ATmega169P 32. Ordering Information Speed (MHz)(3) Power Supply 8 16 Notes: Ordering Code Package(1)(2) Operation Range 1.8V - 5.5V ATmega169PV-8AU ATmega169PV-8MU ATmega169PV-8MCH 64A 64M1 64MC Industrial (-40°C to 85°C) 2.7V - 5.5V ATmega169P-16AU ATmega169P-16MU ATmega169P-16MCH 64A 64M1 64MC Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega169P 33. Packaging Information 33.1 64A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 SYMBOL Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion.
ATmega169P 33.2 64M1 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. SYMBOL MIN A 0.80 0.90 1.00 A1 – 0.02 0.05 b 0.18 0.25 0.30 D 8.90 9.00 9.
ATmega169P 33.3 64MC C Pin 1 ID D SIDE VIEW y A1 E A TOP VIEW eT eT/2 L eR A26 A34 B23 B30 COMMON DIMENSIONS (Unit of Measure = mm) A1 A25 B1 B22 R0.20 0.40 b D2 SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.28 C eT B7 B16 A8 A18 A9 A17 L (0.18) REF B8 B15 E2 K BOTTOM VIEW 1. The terminal #1 ID is a Laser-marked Feature. Note: Package Drawing Contact: packagedrawings@atmel.com (0.1) REF NOTE 0.20 REF D 6.90 7.00 7.10 D2 3.
ATmega169P 34. Errata 34.1 ATmega169P Rev. G No known errata. 34.2 ATmega169P Rev. A to F Not sampled.
ATmega169P 35. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 35.1 Rev. 8018P 08/10 1. 2. 3. 35.2 Rev. 8018O 10/09 1. 2. 35.3 35.5 35.6 Changed datasheet status to “Mature” Added Capacitance for Low-frequency Crystal Oscillator, Table 8-5 on page 33. Rev. 8018N 08/09 1. 35.
ATmega169P 35.7 35.8 35.9 10. 11. 12. Replaced Figure 29-36 on page 357 by a correct one. Updated ”Ordering Information” on page 380. Added ”64MC” on page 383 package to ”Packaging Information” on page 381. 1. 2. 3. Updated ”Features” on page 1. Added ”Minimizing Power Consumption” on page 237 in the LCD section. Updated ”System and Reset Characteristics” on page 333. 1. 2. 3. Updated ”Low-frequency Crystal Oscillator” on page 34.
ATmega169P 35.13 Rev. D 07/06 1. 2. 3. 4. 5 6. 7. 8. 9. Updated ”Register Description for I/O-Ports” on page 88. Updated ”Fast PWM Mode” on page 97. Updated ”Fast PWM Mode” on page 120. Updated Table 14-2 on page 102, Table 14-4 on page 103, Table 15-3 on page 129, Table 15-4 on page 130, Table 17-2 on page 153 and Table 17-4 on page 154. Updated ”UCSRnC – USART Control and Status Register n C” on page 196. Updated Features in ”USI – Universal Serial Interface” on page 199.
ATmega169P Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1Pinout - TQFP/QFN/MLF ...........................................................................................2 1.2Pinout - DRQFN ........................................................................................................3 2 Overview .......
ATmega169P 8.6Low-frequency Crystal Oscillator .............................................................................34 8.7External Clock .........................................................................................................36 8.8Timer/Counter Oscillator .........................................................................................37 8.9Clock Output Buffer .................................................................................................37 8.
ATmega169P 14.1Features ................................................................................................................91 14.2Overview ...............................................................................................................91 14.3Timer/Counter Clock Sources ...............................................................................92 14.4Counter Unit ..........................................................................................................92 14.
ATmega169P 17.9Timer/Counter Prescaler .....................................................................................152 17.108-bit Timer/Counter Register Description ..........................................................153 18 SPI – Serial Peripheral Interface ......................................................... 158 18.1Features ..............................................................................................................158 18.2Overview ....................................
ATmega169P 22.6Changing Channel or Reference Selection .........................................................221 22.7ADC Noise Canceler ...........................................................................................222 22.8ADC Conversion Result ......................................................................................227 22.9ADC Register Description ...................................................................................229 23 LCD Controller ...........................
ATmega169P 26.6Entering the Boot Loader Program ......................................................................285 26.7Addressing the Flash During Self-Programming .................................................286 26.8Self-Programming the Flash ................................................................................287 26.9Register Description ............................................................................................294 27 Memory Programming .............................
ATmega169P 29.12Current Consumption of Peripheral Units ..........................................................368 29.13Current Consumption in Reset and Reset Pulsewidth ......................................371 30 Register Summary ............................................................................... 373 31 Instruction Set Summary .................................................................... 377 32 Ordering Information ....................................................................
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