Datasheet

46
2545T–AVR–05/11
ATmega48/88/168
Figure 11-1. Reset logic.
11.3 Power-on reset
A power-on reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in “System and reset characteristics” on page 307. The POR is activated whenever
V
CC
is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A power-on reset (POR) circuit ensures that the device is reset from power-on. Reaching the
power-on reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
CC
rise. The RESET signal is activated again, without any delay,
when V
CC
decreases below the detection level.
Figure 11-2. MCU start-up, RESET
tied to V
CC.
MCU status
register (MCUSR)
Brown-out
reset circuit
BODLEVEL [2..0]
Delay counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BU S
Clock
generator
SPIKE
FILTER
Pull-up resistor
Watchdog
oscillator
SUT[1:0]
Power-on reset
circuit
RSTDISBL
Watchdog
timer
Reset circuit
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC