Datasheet
368
2545T–AVR–05/11
ATmega48/88/168
36.18 Rev. 2545C-04/04
36.19 Rev. 2545B-01/04
4. Moved “TIMSK2 – Timer/Counter2 interrupt mask register” on page 158 and
“TIFR2 – Timer/Counter2 interrupt flag register” on page 158 to
“Register description” on page 153.
5. Updated cross-reference in “Electrical interconnection” on page 210.
6. Updated equation in “Bit rate generator unit” on page 216.
7. Added “Page size” on page 289.
8. Updated “Serial programming algorithm” on page 299.
9. Updated Ordering Information for “Atmel ATmega168” on page 352.
10. Updated “Errata Atmel ATmega88” on page 360 and “Errata Atmel ATmega168” on
page 361.
11. Updated equation in “Bit rate generator unit” on page 216.
1. Speed Grades changed: 12MHz to 10MHz and 24MHz to 20MHz
2. Updated “Speed grades” on page 305.
3. Updated “Ordering information” on page 350.
4. Updated “Errata Atmel ATmega88” on page 360.
1. Added PDIP to “I/O and Packages”, updated “Speed Grade” and Power Consumption
Estimates in 36.“Features” on page 1.
2. Updated “Stack pointer” on page 13 with RAMEND as recommended Stack Pointer
value.
3. Added section “Power reduction register” on page 41 and a note regarding the use of
the PRR bits to 2-wire, Timer/Counters, USART, Analog Comparator and ADC
sections.
4. Updated “Watchdog timer” on page 49.
5. Updated Figure 16-2 on page 130 and Table 16-3 on page 131.
6. Extra Compare Match Interrupt OCF2B added to features in section “8-bit
Timer/Counter2 with PWM and asynchronous operation” on page 140
7. Updated Table 10-1 on page 39, Table 24-5 on page 259, Table 28-4 to Table 28-7
on page 286 to 288 and Table 24-1 on page 249. Added note 2 to Table 28-1 on page
285. Fixed typo in Table 13-1 on page 67.
8. Updated whole “Typical characteristics” on page 315.
9. Added item 2 to 5 in “Errata Atmel ATmega48” on page 357.
10. Renamed the following bits:
- SPMEN to SELFPRGEN
- PSR2 to PSRASY
- PSR10 to PSRSYNC
- Watchdog Reset to Watchdog System Reset
11. Updated C code examples containing old IAR syntax.
12. Updated BLBSET description in “SPMCSR – Store program memory control and sta-
tus register” on page 283.