Datasheet

310
2545T–AVR–05/11
ATmega48/88/168
Figure 29-5. SPI interface timing requirements (master mode).
Figure 29-6. SPI interface timing requirements (slave mode).
MOSI
(Data output)
SCK
(CPOL = 1)
MISO
(Data input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
61
22
345
8
7
MISO
(Data output)
SCK
(CPOL = 1)
MOSI
(Data input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16