Datasheet

309
2545T–AVR–05/11
ATmega48/88/168
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency.
5. This requirement applies to all Atmel ATmega48/88/168 2-wire Serial Interface operation. Other devices connected to the 2-
wire Serial Bus need only obey the general f
SCL
requirement.
Figure 29-4. 2-wire serial bus timing.
29.7 SPI timing characteristics
See Figure 29-5 on page 310 and Figure 29-6 on page 310 for details.
Note: 1. In SPI programming mode the minimum SCK high/low period is:
- 2 t
CLCL
for f
CK
< 12MHz
- 3 t
CLCL
for f
CK
> 12MHz
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r
Table 29-6. SPI timing parameters.
Description Mode Minimum Typical Maximum
1 SCK period Master
See Table 19-5
on page 169
ns
2 SCK high/low Master 50% duty cycle
3 Rise/fall time Master 3.6
4 Setup Master 10
5Hold Master 10
6 Out to SCK Master 0.5 • t
sck
7 SCK to out Master 10
8 SCK to out high Master 10
9SS low to out Slave 15
10 SCK period Slave 4 • t
ck
11 SCK high/low
(1)
Slave 2 • t
ck
12 Rise/fall time Slave 1600
13 Setup Slave 10
14 Hold Slave t
ck
15 SCK to out Slave 15
16 SCK to SS
high Slave 20
17 SS high to tri-state Slave 10
18 SS
low to SCK Slave 20