Datasheet

308
2545T–AVR–05/11
ATmega48/88/168
29.6 2-wire serial interface characteristics
Table 29-5 describes the requirements for devices connected to the 2-wire Serial Bus. The Atmel ATmega48/88/168 2-wire
Serial Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 29-4 on page 309.
Notes: 1. In ATmega48/88/168, this parameter is characterized and not 100% tested.
2. Required only for f
SCL
> 100kHz.
Table 29-5. 2-wire serial bus requirements.
Symbol Parameter
Condition Min. Max. Units
V
IL
Input low-voltage -0.5 0.3V
CC
V
V
IH
Input high-voltage 0.7V
CC
V
CC
+ 0.5
V
hys
(1)
Hysteresis of schmitt trigger inputs 0.05V
CC
(2)
–
V
OL
(1)
Output low-voltage 3mA sink current 0 0.4
tr
(1)
Rise time for both SDA and SCL 20 + 0.1C
b
(3)(2)
300
ns
tof
(1)
Output fall time from V
IHmin
to V
ILmax
10pF < C
b
< 400pF
(3)
20 + 0.1C
b
(3)(2)
250
tSP
(1)
Spikes suppressed by input filter 0 50
(2)
I
i
Input current each I/O pin 0.1V
CC
< V
i
< 0.9V
CC
-10 10 µA
C
i
(1)
Capacitance for each I/O pin – 10 pF
f
SCL
SCL clock frequency f
CK
(4)
> max(16f
SCL
, 250kHz)
(5)
0 400 kHz
Rp Value of pull-up resistor
f
SCL
≤ 100kHz
f
SCL
> 100kHz
t
HD;STA
Hold time (repeated) START condition
f
SCL
≤ 100kHz 4.0 –
µs
f
SCL
> 100kHz 0.6 –
t
LOW
Low period of the SCL clock
f
SCL
≤ 100kHz 4.7 –
f
SCL
> 100kHz 1.3 –
t
HIGH
High period of the SCL clock
f
SCL
≤ 100kHz 4.0 –
f
SCL
> 100kHz 0.6 –
t
SU;STA
Setup time for a repeated START condition
f
SCL
≤ 100kHz 4.7 –
f
SCL
> 100kHz 0.6 –
t
HD;DAT
Data hold time
f
SCL
≤ 100kHz 0 3.45
f
SCL
> 100kHz 0 0.9
t
SU;DAT
Data setup time
f
SCL
≤ 100kHz 250 –
ns
f
SCL
> 100kHz 100 –
t
SU;STO
Setup time for STOP condition
f
SCL
≤ 100kHz 4.0 –
µs
f
SCL
> 100kHz 0.6 –
t
BUF
Bus free time between a STOP and START
condition
f
SCL
≤ 100kHz 4.7 –
f
SCL
> 100kHz 1.3 –
V
CC
0.4V–
3mA
----------------------------
1000ns
C
b
-----------------
Ω
V
CC
0.4V–
3mA
----------------------------
300ns
C
b
--------------