Datasheet
283
2545T–AVR–05/11
ATmega48/88/168
Note: 1. Z15:Z14: Always ignored.
Z0: Should be zero for all SPM commands, byte select for the LPM instruction.
See “Addressing the flash during self-programming” on page 274 for details about the use of
Z-pointer during Self-Programming.
27.9 Register description
27.9.1 SPMCSR – Store program memory control and status register
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
• Bit 7 – SPMIE: SPM interrupt enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-
PRGEN bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-while-write section busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.
Table 27-11. Explanation of different variables used in Figure 27-3 on page 275 and the map-
ping to the Z-pointer, Atmel ATmega168.
Variable
Corresponding
Z-value
(1)
Description
PCMSB 12
Most significant bit in the Program Counter. (The
program counter is 12 bits PC[11:0])
PAG EM SB 5
Most significant bit which is used to address the
words within one page (64 words in a page requires
6 bits PC [5:0])
ZPCMSB Z13
Bit in Z-register that is mapped to PCMSB. Because
Z0 is not used, the ZPCMSB equals PCMSB + 1
ZPAGEMSB Z6
Bit in Z-register that is mapped to PAGEMSB.
Because Z0 is not used, the ZPAGEMSB equals
PAGEMSB + 1
PCPAGE PC[12:6] Z13:Z7
Program counter page address: Page select, for
page erase and page write
PCWORD PC[5:0] Z6:Z1
Program counter word address: Word select, for
filling temporary buffer (must be zero during page
write operation)
Bit 7 6 5 4 3 2 1 0
0x37 (0x57)
SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SELFPRGEN SPMCSR
Read/write R/W R R R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0