Datasheet

248
2545T–AVR–05/11
ATmega48/88/168
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see Table 24-1 on page
249.
Figure 24-4. ADC timing diagram, first conversion (single conversion mode).
Figure 24-5. ADC timing diagram, single conversion.
Figure 24-6. ADC timing diagram, auto triggered conversion.
Sign and MSB of result
LSB of result
ADC clock
ADSC
Sample & hold
ADIF
ADCH
ADCL
Cycle number
ADEN
1 212
13
14 15
16 17
18 19 20 21 22 23
24 25
1 2
First conversion
Next
conversion
3
MUX and REFS
update
MUX and REFS
update
Conversion
complete
1
2 3 4 5 6 7 8
9 10 11 12 13
Sign and MSB of result
LSB of result
ADC clock
ADSC
ADIF
ADCH
ADCL
Cycle number
12
One conversion Next conversion
3
Sample & hold
MUX and REFS
update
Conversion
complete
MUX and REFS
update
1 2 3 4 5 6 7 8
9
10 11 12 13
Sign and MSB of result
LSB of result
ADC clock
Trigger
source
ADIF
ADCH
ADCL
Cycle number
12
One conversion Next conversion
Conversion
complete
Prescaler
reset
ADATE
Prescaler
reset
Sample &
hold
MUX and REFS
update