Datasheet
210
2545T–AVR–05/11
ATmega48/88/168
The PRTWI bit in “Minimizing power consumption” on page 41 must be written to zero to enable
the 2-wire serial interface.
22.2.2 Electrical interconnection
As depicted in Figure 22-1 on page 209, both bus lines are connected to the positive supply volt-
age through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or
open-collector. This implements a wired-AND function which is essential to the operation of the
interface. A low level on a TWI bus line is generated when one or more TWI devices output a
zero. A high level is output when all TWI devices tri-state their outputs, allowing the pull-up resis-
tors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered
in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400pF and the 7-bit slave address space. A detailed specification of the electrical charac-
teristics of the TWI is given in “2-wire serial interface characteristics” on page 308. Two different
sets of specifications are presented there, one relevant for bus speeds below 100kHz, and one
valid for bus speeds up to 400kHz.
22.3 Data transfer and frame format
22.3.1 Transferring bits
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 22-2. Data validity.
22.3.2 START and STOP conditions
The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
Slave The device addressed by a master.
Transmitter The device placing data on the bus.
Receiver The device reading data from the bus.
Table 22-1. TWI terminology.
Term Description
SDA
SCL
Data stable Data stable
Data change