Datasheet

200
2545T–AVR–05/11
ATmega48/88/168
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).
BAUD Baud rate (in bits per second, bps)
f
OSC
System Oscillator clock frequency
UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095)
21.4 SPI data modes and timing
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in Figure 21-1 on page 201. Data bits are shifted out and latched in on opposite edges of
the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and
UCPHAn functionality is summarized in Table 21-2. Note that changing the setting of any of
these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Table 21-1. Equations for calculating baud rate register setting.
Operating mode
Equation for calculating baud
rate
(1)
Equation for calculating UBRRn
value
Synchronous Master
mode
BAUD
f
OSC
2 UBRRn 1+()
---------------------------------------=
UBRRn
f
OSC
2BAUD
-------------------- 1–=
Table 21-2. UCPOLn and UCPHAn functionality.
UCPOLn UCPHAn SPI mode Leading edge Trailing edge
0 0 0 Sample (rising) Setup (falling)
0 1 1 Setup (rising) Sample (falling)
1 0 2 Sample (falling) Setup (rising)
1 1 3 Setup (falling) Sample (rising)