Datasheet

173
2545T–AVR–05/11
ATmega48/88/168
Figure 20-2. Clock generation logic, block diagram.
Signal description:
tx
clk
Transmitter clock (internal signal).
rx
clk
Receiver base clock (internal signal).
x
cki
Input from XCK pin (internal signal). Used for synchronous slave
operation.
x
cko
Clock output to XCK pin (internal signal). Used for synchronous master
operation.
f
osc
System clock frequency.
20.3.1 Internal clock generation – The baud rate generator
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to Figure 20-2.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
osc
), is loaded with the UBRRn value each time the counter has counted down to zero or when
the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
osc
/(UBRRn+1)). The Transmitter divides the
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
Prescaling
down-counter
/2
UBRRn
/4 /2
foscn
UBRRn+1
Sync
register
OSC
XCKn
pin
txclk
U2Xn
UMSELn
DDR_XCKn
0
1
0
1
xcki
xcko
DDR_XCKn
rxclk
0
1
1
0
Edge
detector
UCPOLn