Datasheet

158
2545T–AVR–05/11
ATmega48/88/168
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2A pin.
18.11.5 OCR2B – Output compare register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2B pin.
18.11.6 TIMSK2 – Timer/Counter2
interrupt mask register
• Bit 2 – OCIE2B: Timer/Counter2 output compare match B interrupt enable
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, that is, when the OCF2B bit is set in the
Timer/Counter 2 Interrupt Flag Register – TIFR2.
• Bit 1 – OCIE2A: Timer/Counter2 output compare match A interrupt enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, that is, when the OCF2A bit is set in the
Timer/Counter 2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 overflow interrupt enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, that is, when the TOV2 bit is set in the Timer/Counter2 Inter-
rupt Flag Register – TIFR2.
18.11.7 TIFR2 – Timer/Counter2 interrupt flag register
• Bit 2 – OCF2B: Output compare flag 2 B
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt
Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.
Bit 76543210
(0xB4) OCR2B[7:0] OCR2B
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543 2 1 0
(0x70) –––––OCIE2BOCIE2ATOIE2TIMSK2
Read/write RRRRR R/WR/WR/W
Initial value 00000 0 0 0
Bit 76543210
0x17 (0x37) –––––OCF2BOCF2ATOV2TIFR2
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0