Datasheet

133
2545T–AVR–05/11
ATmega48/88/168
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform generation mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure
16-10 on page 127 and Figure 16-11 on page 128.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
16.11.3 TCCR1C – Timer/Counter1 control register C
• Bit 7 – FOC1A: Force output compare for channel A
• Bit 6 – FOC1B: Force output compare for channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode..
When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on
the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0
bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the
value present in the COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
Table 16-5. Clock select bit description.
CS12 CS11 CS10 Description
0 0 0 No clock source (timer/counter stopped)
001clk
I/O
/1 (no prescaling)
010clk
I/O
/8 (from prescaler)
011clk
I/O
/64 (from prescaler)
100clk
I/O
/256 (from prescaler)
101clk
I/O
/1024 (from prescaler)
1 1 0 External clock source on T1 pin. Clock on falling edge.
1 1 1 External clock source on T1 pin. Clock on rising edge.
Bit 7 6 5 4 3 2 1 0
(0x82) FOC1A FOC1B – – – – – – TCCR1C
Read/write R/W R/W R R R R R R
Initial value 0 0 0 0 0 0 0 0