Datasheet

100
2545T–AVR–05/11
ATmega48/88/168
Figure 15-10. Timer/counter timing diagram, setting of OCF0x, with prescaler (f
clk_I/O
/8).
Figure 15-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
PWM mode where OCR0A is TOP.
Figure 15-11. Timer/counter timing diagram, clear timer on compare match mode, with pres-
caler (f
clk_I/O
/8).
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)