Datasheet

13. System Clock and Clock Options

13.1 Clock Systems and Their Distribution

The following figure illustrates the principal clock systems in the device and their distribution. All the

clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes. The clock systems are described in the

following sections.

The system clock frequency refers to the frequency generated from the system clock prescaler. All clock

outputs from the AVR clock control unit runs in the same frequency.

Figure 13-1. Clock Distribution

Watchdog

Oscillator

ATmega48PA/88PA/168PA

System Clock and Clock Options

Datasheet Complete

DS40002011A-page 53