Datasheet

2 – TWI data setup time can be too short

When running the device as a TWI slave with a system clock above 2 MHz,

the data setup time for the first bit after ACK may in some cases be too

short. This may cause a false start or stop condition on the TWI line.

Fix/Workaround:

Insert a delay between setting TWDR and TWCR.

38.3.5 Rev. A to D

Not sampled.

ATmega48PA/88PA/168PA

Errata

Datasheet Complete

DS40002011A-page 489