Datasheet

Offset Name Bit Pos.
0x84
TCNT1L and
TCNT1H
7:0 TCNT1[7:0]
15:8 TCNT1[15:8]
0x86 ICR1L and ICR1H
7:0 ICR1[7:0]
15:8 ICR1[15:8]
0x88
OCR1AL and
OCR1AH
7:0 OCR1A[7:0]
15:8 OCR1A[15:8]
0x8A
OCR1BL and
OCR1BH
7:0 OCR1B[7:0]
15:8 OCR1B[15:8]
0x8C
...
0xAF
Reserved
0xB0 TCCR2A 7:0 COM2A[1:0] COM2B[1:0] WGM2[1:0]
0xB1 TCCR2B 7:0 FOC2A FOC2B WGM22 CS2[2:0]
0xB2 TCNT2 7:0 TCNT2[7:0]
0xB3 OCR2A 7:0 OCR2A[7:0]
0xB4 OCR2B 7:0 OCR2B[7:0]
0xB5 Reserved
0xB6 ASSR 7:0 EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB
0xB7 Reserved
0xB8 TWBR 7:0 TWBR [7:0]
0xB9 TWSR 7:0 TWS7 TWS6 TWS5 TWS4 TWS3 TWPS[1:0]
0xBA TWAR 7:0 TWA[6:0] TWGCE
0xBB TWDR 7:0 TWD[7:0]
0xBC TWCR 7:0 TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE
0xBD TWAMR 7:0 TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0
0xBE
...
0xBF
Reserved
0xC0 UCSR0A 7:0 RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0
0xC1 UCSR0B 7:0 RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80
0xC2 UCSR0C 7:0 UMSEL0 [1:0] UPM0 [1:0] USBS0
UCSZ01 /
UDORD0
UCSZ00 /
UCPHA0
UCPOL0
0xC3 Reserved
0xC4
UBRR0L and
UBRR0H
7:0 UBRR0[7:0]
15:8 UBRR0[11:8]
0xC6 UDR0 7:0 TXB / RXB[7:0]
35.1 Note
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved
I/O memory addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI
instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC
instructions.
3. Some of the Status flags are cleared by writing a logical one to them. Note that, unlike most other
AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used
ATmega48PA/88PA/168PA
Register Summary
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 474