Datasheet

12.6.4 EEPROM Control Register

Name: EECR

Offset: 0x3F [ID-000004d0]

Reset: 0x00

Property: When addressing as I/O register: address offset is 0x1F

Bit 7 6 5 4 3 2 1 0

EEPM[1:0] EERIE EEMPE EEPE EERE

Access

R/W R/W R/W R/W R/W R/W

Reset x x 0 0 x 0

Bits 5:4 – EEPM[1:0] EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action will be triggered when

writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the

new value) or to split the erase and write operations into two different operations. The programming times

for the different modes are shown in the table below. While EEPE is set, any write to EEPMn will be

ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 12-1. EEPROM Mode Bits

EEPM[1:0] Typ. Programming Time Operation

00 3.4ms Erase and Write in one operation (Atomic Operation)

01 1.8ms Erase Only

10 1.8ms Write Only

11 - Reserved for future use

Bit 3 – EERIE EEPROM Ready Interrupt Enable

Writing EERIE to '1' enables the EEPROM ready interrupt if the I bit in SREG is set. Writing EERIE to

zero disables the interrupt. The EEPROM ready interrupt generates a constant interrupt when EEPE is

cleared. The interrupt will not be generated during EEPROM write or SPM.

Bit 2 – EEMPE EEPROM Master Write Enable

The EEMPE bit determines whether writing EEPE to '1' causes the EEPROM to be written.

When EEMPE is '1', setting EEPE within four clock cycles will write data to the EEPROM at the selected

address.

If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to '1' by software,

hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an

EEPROM write procedure.

Bit 1 – EEPE EEPROM Write Enable

The EEPROM write enable signal EEPE is the write strobe to the EEPROM. When address and data are

correctly set up, the EEPE bit must be written to '1' to write the value into the EEPROM. The EEMPE bit

must be written to '1' before EEPE is written to '1', otherwise, no EEPROM write takes place. The

following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not

essential):

ATmega48PA/88PA/168PA

AVR Memories

Datasheet Complete

DS40002011A-page 47