Datasheet

12.6.3 EEPROM Data Register

Name: EEDR

Offset: 0x40 [ID-000004d0]

Reset: 0x00

Property: When addressing as I/O Register: address offset is 0x20

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

Bit 7 6 5 4 3 2 1 0

EEDR[7:0]

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – EEDR[7:0] EEPROM Data

For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in

the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data

read out from the EEPROM at the address given by EEAR.

ATmega48PA/88PA/168PA

AVR Memories

Datasheet Complete

DS40002011A-page 46